From: York Sun <yorksun@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 10/31] powerpc/mpc8xxx: Add T1040 and variant SoCs
Date: Fri, 22 Mar 2013 10:29:08 -0700 [thread overview]
Message-ID: <1363973369-26110-10-git-send-email-yorksun@freescale.com> (raw)
In-Reply-To: <1363973369-26110-1-git-send-email-yorksun@freescale.com>
T1040 and variants have e5500 cores and are compliant to QorIQ Chassis
Generation 2. The major difference between T1040 and its variants is the
number of cores and the number of L2 switch ports.
Signed-off-by: York Sun <yorksun@freescale.com>
---
arch/powerpc/cpu/mpc85xx/Makefile | 3 +
.../cpu/mpc85xx/{b4860_ids.c => t1040_ids.c} | 14 +--
arch/powerpc/cpu/mpc85xx/t1040_serdes.c | 94 ++++++++++++++++++++
arch/powerpc/cpu/mpc8xxx/cpu.c | 6 ++
arch/powerpc/include/asm/config_mpc85xx.h | 26 ++++++
arch/powerpc/include/asm/fsl_serdes.h | 8 ++
arch/powerpc/include/asm/immap_85xx.h | 5 ++
arch/powerpc/include/asm/processor.h | 6 ++
8 files changed, 149 insertions(+), 13 deletions(-)
copy arch/powerpc/cpu/mpc85xx/{b4860_ids.c => t1040_ids.c} (90%)
create mode 100644 arch/powerpc/cpu/mpc85xx/t1040_serdes.c
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 6e5aec2..2318064 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -88,6 +88,7 @@ COBJS-$(CONFIG_PPC_B4420) += ddr-gen3.o
COBJS-$(CONFIG_PPC_B4860) += ddr-gen3.o
COBJS-$(CONFIG_BSC9131) += ddr-gen3.o
COBJS-$(CONFIG_BSC9132) += ddr-gen3.o
+COBJS-$(CONFIG_PPC_T1040) += ddr-gen3.o
COBJS-$(CONFIG_CPM2) += ether_fcc.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
@@ -106,6 +107,7 @@ COBJS-$(CONFIG_PPC_T4240) += t4240_ids.o
COBJS-$(CONFIG_PPC_T4160) += t4240_ids.o
COBJS-$(CONFIG_PPC_B4420) += b4860_ids.o
COBJS-$(CONFIG_PPC_B4860) += b4860_ids.o
+COBJS-$(CONFIG_PPC_T1040) += t1040_ids.o
COBJS-$(CONFIG_QE) += qe_io.o
COBJS-$(CONFIG_CPM2) += serial_scc.o
@@ -143,6 +145,7 @@ COBJS-$(CONFIG_PPC_T4160) += t4240_serdes.o
COBJS-$(CONFIG_PPC_B4420) += b4860_serdes.o
COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o
COBJS-$(CONFIG_BSC9132) += bsc9132_serdes.o
+COBJS-$(CONFIG_PPC_T1040) += t1040_serdes.o
COBJS-y += cpu.o
COBJS-y += cpu_init.o
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c
similarity index 90%
copy from arch/powerpc/cpu/mpc85xx/b4860_ids.c
copy to arch/powerpc/cpu/mpc85xx/t1040_ids.c
index 0f4e82e..ed61599 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c
@@ -55,13 +55,11 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
};
#endif
-#ifdef CONFIG_SYS_SRIO
struct srio_liodn_id_table srio_liodn_tbl[] = {
SET_SRIO_LIODN_1(1, 307),
SET_SRIO_LIODN_1(2, 387),
};
int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
-#endif
struct liodn_id_table liodn_tbl[] = {
#ifdef CONFIG_SYS_DPAA_QBMAN
@@ -73,17 +71,15 @@ struct liodn_id_table liodn_tbl[] = {
SET_USB_LIODN(1, "fsl-usb2-mph", 553),
- SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
+ SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 148),
SET_DMA_LIODN(1, 147),
SET_DMA_LIODN(2, 227),
-#ifndef CONFIG_PPC_B4420
SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
-#endif
/* SET_NEXUS_LIODN(557), -- not yet implemented */
};
@@ -97,10 +93,8 @@ struct liodn_id_table fman1_liodn_tbl[] = {
SET_FMAN_RX_1G_LIODN(1, 3, 91),
SET_FMAN_RX_1G_LIODN(1, 4, 92),
SET_FMAN_RX_1G_LIODN(1, 5, 93),
-#ifndef CONFIG_PPC_B4420
SET_FMAN_RX_10G_LIODN(1, 0, 94),
SET_FMAN_RX_10G_LIODN(1, 1, 95),
-#endif
};
int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
#endif
@@ -116,12 +110,6 @@ struct liodn_id_table sec_liodn_tbl[] = {
SET_SEC_RTIC_LIODN_ENTRY(d, 551),
SET_SEC_DECO_LIODN_ENTRY(0, 541, 610),
SET_SEC_DECO_LIODN_ENTRY(1, 542, 611),
- SET_SEC_DECO_LIODN_ENTRY(2, 543, 612),
- SET_SEC_DECO_LIODN_ENTRY(3, 544, 613),
- SET_SEC_DECO_LIODN_ENTRY(4, 545, 614),
- SET_SEC_DECO_LIODN_ENTRY(5, 546, 615),
- SET_SEC_DECO_LIODN_ENTRY(6, 547, 616),
- SET_SEC_DECO_LIODN_ENTRY(7, 548, 617),
};
int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
diff --git a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
new file mode 100644
index 0000000..0dc50c0
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet2_serdes.h"
+
+static u8 serdes_cfg_tbl[MAX_SERDES][0xC4][SRDS_MAX_LANES] = {
+ { /* SerDes 1 */
+ [0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
+ PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1},
+ [0x66] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
+ PCIE2, PCIE3, PCIE4, SATA1},
+ [0x67] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
+ PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
+ [0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
+ PCIE2, PCIE2, PCIE2, PCIE2},
+ [0x8D] = {PCIE1, SGMII_SW1_DTSEC3, SGMII_SW1_DTSEC1, SGMII_SW1_DTSEC2,
+ PCIE2, SGMII_SW1_DTSEC6, SGMII_SW1_DTSEC4, SGMII_SW1_DTSEC5},
+ [0x89] = {PCIE1, SGMII_SW1_DTSEC3, SGMII_SW1_DTSEC1, SGMII_SW1_DTSEC2,
+ PCIE2, PCIE3, SGMII_SW1_DTSEC4, SATA1},
+ [0x86] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ PCIE2, PCIE3, PCIE4, SATA1},
+ [0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
+ [0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
+ [0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
+ [0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ PCIE2, PCIE2, PCIE2, PCIE2},
+ [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1,
+ PCIE2, PCIE3, PCIE4, SATA1},
+ [0x08] = {PCIE1, PCIE1, PCIE1, PCIE1,
+ PCIE2, PCIE3, SATA2, SATA1},
+ [0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
+ [0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
+ [0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
+ [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1,
+ PCIE2, PCIE2, PCIE2, PCIE2},
+ },
+ {
+ },
+ {
+ },
+ {
+ },
+};
+
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+
+ return serdes_cfg_tbl[serdes][cfg][lane];
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+ int i;
+
+ if (prtcl > (ARRAY_SIZE(serdes_cfg_tbl[serdes])))
+ return 0;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (serdes_cfg_tbl[serdes][prtcl][i] != NONE)
+ return 1;
+ }
+
+ return 0;
+}
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 0087cd0..23e008e 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -85,6 +85,12 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(G4440, G4440, 0),
CPU_TYPE_ENTRY(B4420, B4420, 0),
CPU_TYPE_ENTRY(B4220, B4220, 0),
+ CPU_TYPE_ENTRY(T1040, T1040, 0),
+ CPU_TYPE_ENTRY(T1041, T1041, 0),
+ CPU_TYPE_ENTRY(T1042, T1042, 0),
+ CPU_TYPE_ENTRY(T1020, T1020, 0),
+ CPU_TYPE_ENTRY(T1021, T1021, 0),
+ CPU_TYPE_ENTRY(T1022, T1022, 0),
CPU_TYPE_ENTRY(BSC9130, 9130, 1),
CPU_TYPE_ENTRY(BSC9131, 9131, 1),
CPU_TYPE_ENTRY(BSC9132, 9132, 2),
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 37eb118..24b9fc9 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -602,6 +602,32 @@
#define CONFIG_SYS_FSL_ERRATUM_A_004934
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+#elif defined(CONFIG_PPC_T1040)
+#define CONFIG_E5500
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
+#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
+#define CONFIG_MAX_CPUS 4
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
+#define CONFIG_SYS_FSL_NUM_LAWS 16
+#define CONFIG_SYS_FSL_SEC_COMPAT 4
+#define CONFIG_SYS_NUM_FMAN 1
+#define CONFIG_SYS_NUM_FM1_DTSEC 5
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV 32
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+
#else
#error Processor type not defined for this platform
#endif
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index 6cd7379..ccb91fb 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -80,6 +80,14 @@ enum srds_prtcl {
XFI_FM2_MAC9,
XFI_FM2_MAC10,
INTERLAKEN,
+ SGMII_SW1_DTSEC1, /* SW indicates on L2 switch */
+ SGMII_SW1_DTSEC2,
+ SGMII_SW1_DTSEC3,
+ SGMII_SW1_DTSEC4,
+ SGMII_SW1_DTSEC5,
+ SGMII_SW1_DTSEC6,
+ QSGMII_SW1_A, /* SW indicates on L2 swtich */
+ QSGMII_SW1_B,
};
enum srds {
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 65d788a..6de8188 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1845,6 +1845,11 @@ typedef struct ccsr_gur {
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
+#elif defined(CONFIG_PPC_T1040)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
#endif
#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000
#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 1760aa1..5799386 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1126,6 +1126,12 @@
#define SVR_G4440 0x868101
#define SVR_B4420 0x868102
#define SVR_B4220 0x868103
+#define SVR_T1040 0x852000
+#define SVR_T1041 0x852001
+#define SVR_T1042 0x852002
+#define SVR_T1020 0x852100
+#define SVR_T1021 0x852101
+#define SVR_T1022 0x852102
#define SVR_8610 0x80A000
#define SVR_8641 0x809000
--
1.7.9.5
next prev parent reply other threads:[~2013-03-22 17:29 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-22 17:28 [U-Boot] [PATCH 01/31] 83xx/pcie: fix build error for 83xx pcie York Sun
2013-03-22 17:29 ` [U-Boot] [PATCH 02/31] Enable L2 cache parity/ECC error checking York Sun
2013-03-22 17:29 ` [U-Boot] [PATCH 03/31] net/phy: fix select line for TN80xx York Sun
2013-03-22 20:59 ` Wolfgang Denk
2013-03-22 17:29 ` [U-Boot] [PATCH 04/31] powerpc/mpc85xx: check if core is disabled for showing status York Sun
2013-03-22 17:29 ` [U-Boot] [PATCH 05/31] powerpc/t4240qds: Add VDD override York Sun
2013-03-22 21:00 ` Wolfgang Denk
2013-03-22 17:29 ` [U-Boot] [PATCH 06/31] T4240/ramboot: enable PBL tool for T4240 York Sun
2013-03-22 17:29 ` [U-Boot] [PATCH 07/31] Add e6500 L2 replacement policy selection York Sun
2013-03-22 21:00 ` Wolfgang Denk
2013-03-22 17:29 ` [U-Boot] [PATCH 08/31] powerpc/p5040: enable NAND, SD, SPI boot support York Sun
2013-03-22 17:29 ` [U-Boot] [PATCH 09/31] powerpc/T4160: Merge T4160 and T4240 in config_mpc85xx.h York Sun
2013-03-22 17:29 ` York Sun [this message]
2013-03-22 21:00 ` [U-Boot] [PATCH 10/31] powerpc/mpc8xxx: Add T1040 and variant SoCs Wolfgang Denk
2013-03-22 17:29 ` [U-Boot] [PATCH 11/31] powerpc/chassis2: Change core numbering scheme York Sun
2013-03-22 17:29 ` [U-Boot] [PATCH 12/31] powerpc/mpc8xxx: Allow DDR overclock York Sun
2013-03-22 17:29 ` [U-Boot] [PATCH 13/31] powerpc/qixis: add clock measurement registers York Sun
2013-03-22 17:29 ` [U-Boot] [PATCH 14/31] powerpc/t4qds: use clock measurement for sysclk and ddr clock York Sun
2013-03-22 21:01 ` Wolfgang Denk
2013-03-22 17:29 ` [U-Boot] [PATCH 15/31] powerpc/p5040: enable PBL tool support York Sun
2013-03-22 17:29 ` [U-Boot] [PATCH 16/31] board/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32M York Sun
2013-03-22 17:29 ` [U-Boot] [PATCH 17/31] Enable XAUI interface for B4860QDS York Sun
2013-03-22 21:02 ` Wolfgang Denk
2013-03-22 17:29 ` [U-Boot] [PATCH 18/31] powerpc/t4qds: Add SW7[4] in the DIP switch display York Sun
2013-03-22 21:02 ` Wolfgang Denk
2013-03-22 17:29 ` [U-Boot] [PATCH 19/31] powerpc/t4qds: Enable master module for Boot from SRIO and PCIE York Sun
2013-03-22 17:29 ` [U-Boot] [PATCH 20/31] powerpc/t4qds: Slave module for boot " York Sun
2013-03-22 21:02 ` Wolfgang Denk
2013-03-22 17:29 ` [U-Boot] [PATCH 21/31] powerpc/t4240qds: fix PHY reset timeout issue York Sun
2013-03-22 17:29 ` [U-Boot] [PATCH 22/31] powerpc/doc: Fix the misalignment of document README.srio-pcie-boot-corenet York Sun
2013-03-22 17:29 ` [U-Boot] [PATCH 23/31] powerpc/b4860: fix for Serdes connectivity to SFP's York Sun
2013-03-22 17:29 ` [U-Boot] [PATCH 24/31] powerpc/mpc85xx: add setting of clock-frequency for mpic node York Sun
2013-03-22 21:03 ` Wolfgang Denk
2013-03-22 17:29 ` [U-Boot] [PATCH 25/31] powerpc/p2041: fix serdes reference clock frequency display for PC board York Sun
2013-03-22 21:03 ` Wolfgang Denk
2013-03-22 17:29 ` [U-Boot] [PATCH 26/31] sf: spansion: Add support for S25FL128S York Sun
2013-03-22 17:29 ` [U-Boot] [PATCH 27/31] powerpc/B4: Merge B4420 and B4860 in config_mpc85xx.h York Sun
2013-03-22 17:29 ` [U-Boot] [PATCH 28/31] powerpc/p5040: fix mdio mux for 10G port York Sun
2013-03-22 17:29 ` [U-Boot] [PATCH 29/31] powerpc/usb: Fix usb device-tree fix-up York Sun
2013-03-22 21:04 ` Wolfgang Denk
2013-03-22 17:29 ` [U-Boot] [PATCH 30/31] fman/mEMAC: set SETSP bit in IF_MODE regisgter for RGMII speed York Sun
2013-03-22 17:29 ` [U-Boot] [PATCH 31/31] powerpc/b4860qds: Add LAW Target ID and Create LAW entry for Maple York Sun
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