From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Fri, 22 Mar 2013 10:29:10 -0700 Subject: [U-Boot] [PATCH 12/31] powerpc/mpc8xxx: Allow DDR overclock In-Reply-To: <1363973369-26110-1-git-send-email-yorksun@freescale.com> References: <1363973369-26110-1-git-send-email-yorksun@freescale.com> Message-ID: <1363973369-26110-12-git-send-email-yorksun@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Allow DDR clock runs faster than SPD specifes. This may cause memory failure, but the user should know what is going to happen when using higher than expected DDR clock. Signed-off-by: Ed Swarthout Signed-off-by: York Sun --- .../cpu/mpc8xxx/ddr/lc_common_dimm_params.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c index 9adde31..e958e13 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c @@ -44,7 +44,6 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params, printf("DDR clock (MCLK cycle %u ps) is faster than " "the slowest DIMM(s) (tCKmin %u ps) can support.\n", mclk_ps, tCKmin_X_ps); - return 1; } /* determine the acutal cas latency */ caslat_actual = (tAAmin_ps + mclk_ps - 1) / mclk_ps; @@ -60,7 +59,6 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params, if (caslat_actual * mclk_ps > 20000) { printf("The choosen cas latency %d is too large\n", caslat_actual); - return 1; } outpdimm->lowest_common_SPD_caslat = caslat_actual; -- 1.7.9.5