From: Scott Wood <scottwood@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [v3] command/cache: Add flush command
Date: Mon, 8 Apr 2013 14:05:16 -0500 [thread overview]
Message-ID: <1365447916.28843.7@snotra> (raw)
In-Reply-To: <20130408183513.D80752016C2@gemini.denx.de> (from wd@denx.de on Mon Apr 8 13:35:13 2013)
On 04/08/2013 01:35:13 PM, Wolfgang Denk wrote:
> Dear sun york-R58495,
>
> In message
> <C707E9F4D8007146BF8DC1424B113AC70B3A6A83@039-SN2MPN1-012.039d.mgd.msft.net>
> you wrote:
> >
> > I think it is best to keep this patch as it and stick with the
> > original flush_cache name. It uses the existing function
> > flush_cache() which is available for most (if not all)
> architectures.
> > Splitting the dcache and icache not only adds more code, but
> > architecture-dependent code.
>
> As mentioned before: reusing existing code is fine, but we already
> have commands for cache handling, and adding arbitrary new ones to
> implement combinations of functions makes does not scale. Assume
> tomorrow someone needs to add more ganular handling for example
> regarding L2 caches, etc. Would you suggest to add another set of new
> commands, then? This makes no sense.
Maybe "cache" should be the toplevel command, with "icache" and
"dcache" refactored to be subcommands? Of course, then you're making
an incompatible interface change. How much is consistency worth?
> Please implement IC related operations as subcommands to the "icache"
> command, and DC releated ones as subcommands to "dcache".
The whole point of the patch is to expose the existing flush_cache()
functionality, which is not split into icache/dcache. From the user's
perspective, it's a command to flush the specified region out of *all*
caches. It's an implementation detail that some hardware or
architectures accomplish this using separate dcache and icache
instructions. If you make the interface be "icache/dcache", how would
you handle hardware where the flushing mechanism (or even the cache
itself) is not split?
> [In the example of L2 cache above, it would be for example sufficient
> to add a "-L2" option to the "icache" / "dcache" commands.]
Would it? On our chips L2 cache is (more or less) unified. There's no
separate icache/dcache flush.
-Scott
next prev parent reply other threads:[~2013-04-08 19:05 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-04-05 20:50 [U-Boot] [v3] command/cache: Add flush command York Sun
2013-04-05 21:00 ` Tom Rini
2013-04-05 21:09 ` York Sun
2013-04-05 22:09 ` Wolfgang Denk
2013-04-05 23:02 ` York Sun
2013-04-06 7:01 ` Wolfgang Denk
2013-04-07 3:31 ` sun york-R58495
2013-04-07 8:29 ` Wolfgang Denk
2013-04-08 17:45 ` sun york-R58495
2013-04-08 18:35 ` Wolfgang Denk
2013-04-08 19:05 ` Scott Wood [this message]
2013-04-08 19:18 ` Wolfgang Denk
2013-04-08 19:31 ` Scott Wood
2013-04-09 17:45 ` Wolfgang Denk
2013-04-10 0:58 ` Scott Wood
2013-04-10 2:07 ` [U-Boot] DWMMC / DWMCI question TigerLiu at viatech.com.cn
2013-04-10 11:58 ` Wolfgang Denk
2013-04-11 1:43 ` TigerLiu at viatech.com.cn
2013-04-10 11:54 ` [U-Boot] [v3] command/cache: Add flush command Wolfgang Denk
2013-04-10 19:42 ` Scott Wood
2013-04-10 21:04 ` Wolfgang Denk
2013-04-10 21:10 ` Scott Wood
2013-04-10 22:50 ` Wolfgang Denk
2013-04-10 23:00 ` Scott Wood
2013-04-11 11:56 ` Wolfgang Denk
2013-04-08 19:50 ` Scott Wood
2013-04-09 17:48 ` Wolfgang Denk
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