[U-Boot] [PATCH v8 7/8] arm: faraday: add A360 SoC support

Kuo-Jung Su
2013-12-30T09:23:10Z

This adds board support for the Faraday A360 SoC platform.

Working functions:
- MMU/D-cache
- SD Host controller
- USB EHCI controller
- Network
- I2C EEPROM
- UART

Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
---
Changes for v8:
- Make A360 a standalong changeset.

Changes for v7:
- Update license to use SPDX identifiers.

Changes for v6:
- arch/arm/cpu/faraday/cpu.c:
struct ftwdt010_wdt __iomem *regs -> struct ftwdt010_wdt *regs

Changes for v5:
- Coding Style cleanup:
1. struct chip_regs __iomem *regs -> struct chip_regs *regs
2. Move Faraday specific APIs into asm/arch-faraday/*.h
- Fix Copyright notices (dates) throughout the patch
- Define Faraday machine type in board's config header file
- Add myself as the maintainer for Faraday A360/A369 in MAINTAINERS.
- Drop i2c:FTI2C010 & spi:FTSSP010_SPI support. The corresponding patch
would restart after this patch series have been accepted.
- Revise clock management system

Changes for v4:
- Coding Style cleanup.
- Break-down the interrupt, timers and common utilties.

Changes for v3:
- Coding Style cleanup.
- Drop macros for wirtel()/readl(), call them directly.
- Always insert a blank line between declarations and code.
- Add '__iomem' to all the declaration of HW register pointers.
- a36x_config: No more static global network configurations.
- a36x_config: Add a common file for the redundant configurations.

Changes for v2:
- Coding Style cleanup.
- Use readl(), writel(), clrsetbits_le32() to replace REG() macros.
- Use structure based hardware registers to replace the macro constants.
- Replace BIT() with BIT_MASK().

arch/arm/cpu/faraday/a360/Makefile | 8 +
arch/arm/include/asm/arch-a360/hardware.h | 70 ++++++++
arch/arm/include/asm/arch-a360/sysc.h | 68 ++++++++
arch/arm/include/asm/faraday-common.h | 13 ++
board/faraday/a360evb/Makefile | 9 +
board/faraday/a360evb/board.c | 70 ++++++++
board/faraday/a360evb/clock.c | 62 +++++++
board/faraday/a360evb/lowlevel_init.S | 15 ++
boards.cfg | 1 +
include/common.h | 4 +
include/configs/a360.h | 58 +++++++
include/configs/faraday-common.h | 253 +++++++++++++++++++++++++++++
12 files changed, 631 insertions(+)
create mode 100644 arch/arm/cpu/faraday/a360/Makefile
create mode 100644 arch/arm/include/asm/arch-a360/hardware.h
create mode 100644 arch/arm/include/asm/arch-a360/sysc.h
create mode 100644 arch/arm/include/asm/faraday-common.h
create mode 100644 board/faraday/a360evb/Makefile
create mode 100644 board/faraday/a360evb/board.c
create mode 100644 board/faraday/a360evb/clock.c
create mode 100644 board/faraday/a360evb/lowlevel_init.S
create mode 100644 include/configs/a360.h
create mode 100644 include/configs/faraday-common.h

diff --git a/arch/arm/cpu/faraday/a360/Makefile b/arch/arm/cpu/faraday/a360/Makefile
new file mode 100644
index 0000000..b244f22
--- /dev/null
+++ b/arch/arm/cpu/faraday/a360/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y :=
diff --git a/arch/arm/include/asm/arch-a360/hardware.h b/arch/arm/include/asm/arch-a360/hardware.h
new file mode 100644
index 0000000..7b97a44
--- /dev/null
+++ b/arch/arm/include/asm/arch-a360/hardware.h
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. <http://www.faraday-tech.com/tw/>
+ * Kuo-Jung Su <dantesu@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+
+#define CONFIG_SCU_BASE 0x99900000
+#define CONFIG_PMU_BASE 0x98100000
+#define CONFIG_PMU_IRQ 8
+
+/*
+ * Timer
+ */
+#define CONFIG_FTTMR010_BASE 0x98400000
+#define CONFIG_FTTMR010_IRQ 19
+
+/*
+ * UART
+ */
+#define CONFIG_FTUART010_BASE 0x98200000
+
+/*
+ * Interrupt
+ */
+#define CONFIG_FTINTC020_BASE 0x98800000
+
+/*
+ * WatchDog
+ */
+#define CONFIG_FTWDT010_BASE 0x98500000
+
+/*
+ * NIC
+ */
+#define CONFIG_FTMAC110_BASE 0x90900000
+
+/*
+ * NAND
+ */
+#define CONFIG_FTNANDC020_BASE 0x91000000
+
+/*
+ * I2C
+ */
+#define CONFIG_FTI2C010_BASE 0x98A00000
+
+/*
+ * SPI
+ */
+#define CONFIG_FTSSP010_BASE 0x98B00000
+
+/*
+ * SD/MMC
+ */
+#define CONFIG_FTSDC010_BASE 0x90700000
+
+/*
+ * USB
+ */
+#define CONFIG_FUSBH200_BASE 0x90A00000
+#define CONFIG_FOTG210_BASE 0x90B00000
+
+#endif
diff --git a/arch/arm/include/asm/arch-a360/sysc.h b/arch/arm/include/asm/arch-a360/sysc.h
new file mode 100644
index 0000000..40d4ccf
--- /dev/null
+++ b/arch/arm/include/asm/arch-a360/sysc.h
@@ -0,0 +1,68 @@
+/*
+ * arch/arm/include/asm/arch-a360/sysc.h
+ *
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. <http://www.faraday-tech.com/tw/>
+ * Kuo-Jung Su <dantesu@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_SYSC_H
+#define __ASM_ARCH_SYSC_H
+
+struct sysc_regs {
+ uint32_t idr; /* 0x00: ID Register */
+ uint32_t gcr; /* 0x04: General Control Register */
+ uint32_t ccr; /* 0x08: Clock Configuration Register */
+ uint32_t hcer; /* 0x0C: AHB Clock Enable Register */
+ uint32_t pcer; /* 0x10: APB Clock Enable Register */
+ uint32_t csr; /* 0x14: Configuration Strap Register */
+ uint32_t iomcr[4]; /* IO Mux Control Register */
+ uint32_t iopcr[2]; /* IO Parameter Control Register */
+ uint32_t cescr; /* CPU Edge Sync Control Register */
+ uint32_t expcr[3]; /* PCI-Express Control Register */
+};
+
+#define GCR_LVBC_IRQ3 (1 << 25) /* LVBC interrupt 3 propagation */
+#define GCR_LVBC_IRQ2 (1 << 24) /* LVBC interrupt 2 propagation */
+#define GCR_LVTX_RATE(x) (((x) & 0x1f) << 16) /* LVTX clock rate */
+#define GCR_LVTX_CLK_OUT (1 << 13) /* Enable LVTX clock out */
+#define GCR_USBH1_PLL_ALIVE (1 << 11) /* USB Host PLL alive */
+#define GCR_USBH0_PLL_ALIVE (1 << 10) /* USB Host PLL alive */
+#define GCR_USBH1_CLK_OUT (1 << 9) /* Enable USB Host clock out */
+#define GCR_USBH0_CLK_OUT (1 << 8) /* Enable USB Host clock out */
+#define GCR_DEBUG (1 << 7) /* Enable debug mode */
+#define GCR_DEBUG_SW (1 << 6) /* Enable software debug mode */
+#define GCR_IM (1 << 5) /* Interrupt mask */
+#define GCR_RESET (1 << 4) /* Software reset */
+
+#define CCR_LVDSTX_DSEL(x) (((x) >> 21) & 0x1f) /* LVDS Tx Clock Select */
+#define CCR_LVDSRX_DSEL(x) (((x) >> 16) & 0x1f) /* LVDS Rx Clock Select */
+#define CCR_SSP1_CKFQ(x) (((x) >> 12) & 0xf) /* SSP1 Clock Freq. */
+#define CCR_SSP0_CKFQ(x) (((x) >> 8) & 0xf) /* SSP0 Clock Freq. */
+#define CCR_SSP1_EXTCLK (1 << 7) /* SSP1 use external clock */
+#define CCR_SSP1_PCLK (0 << 7) /* SSP1 use APB clock */
+#define CCR_SSP0_EXTCLK (1 << 6) /* SSP0 use external clock */
+#define CCR_SSP0_PCLK (0 << 6) /* SSP0 use APB clock */
+#define CCR_LVDSTX_HCLK (0 << 4) /* LVDS Tx clock select */
+#define CCR_LVDSTX_PCLK (1 << 4)
+#define CCR_LVDSTX_EXTCLK (2 << 4)
+#define CCR_SDC_HCLK (2 << 2) /* SD/MMC clock select */
+#define CCR_SDC_MCLK (1 << 2)
+#define CCR_SDC_DCLK (0 << 2)
+#define CCR_LCD_EXTCLK (2 << 0) /* LCD clock select */
+#define CCR_LCD_MCLK (1 << 0)
+#define CCR_LCD_HCLK (0 << 0)
+
+#define CSR_PLL_PRESCALE (1 << 9)
+#define CSR_PCIE_MODE1 (1 << 8)
+#define CSR_PCIE_MODE0 (1 << 7)
+#define CSR_DBG_SW (1 << 6)
+#define CSR_DBG_EN (1 << 5)
+#define CSR_NAND_LP (1 << 4) /* NAND: Large Page */
+#define CSR_NAND_AL(x) (((x) >> 2) & 3) /* NAND: Address Length */
+#define CSR_NAND_16X (1 << 1) /* NAND: 16-bits */
+#define CSR_SPIBOOT (1 << 0) /* Boot from SPI(1)/NAND(0) */
+
+#endif
diff --git a/arch/arm/include/asm/faraday-common.h b/arch/arm/include/asm/faraday-common.h
new file mode 100644
index 0000000..e8c4c83
--- /dev/null
+++ b/arch/arm/include/asm/faraday-common.h
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_FARADAY_COMMON_H
+#define _ASM_FARADAY_COMMON_H
+
+ulong clk_get_rate(const char *id);
+
+#endif /* _ASM_FARADAY_COMMON_H */
diff --git a/board/faraday/a360evb/Makefile b/board/faraday/a360evb/Makefile
new file mode 100644
index 0000000..42fef70
--- /dev/null
+++ b/board/faraday/a360evb/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := board.o clock.o
+obj-y += lowlevel_init.o
diff --git a/board/faraday/a360evb/board.c b/board/faraday/a360evb/board.c
new file mode 100644
index 0000000..a2df48d
--- /dev/null
+++ b/board/faraday/a360evb/board.c
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. <http://www.faraday-tech.com/tw/>
+ * Kuo-Jung Su <dantesu@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <spi.h>
+#include <nand.h>
+#include <netdev.h>
+#include <asm/arch/sysc.h>
+#include <faraday/ftsdc010.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct sysc_regs *sysc = (void __iomem *)CONFIG_SCU_BASE;
+
+/*
+ * pinmux
+ */
+static void pinmux_init(void)
+{
+ writel(0x00555500, &sysc->iomcr[3]);
+ setbits_le32(&sysc->iomcr[0], 0x800002AA);
+ setbits_le32(&sysc->iomcr[1], 0x82AAAAAA);
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_early_init_f(void)
+{
+ gd->arch.timer_rate_hz = clk_get_rate("APB");
+ pinmux_init();
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE;
+
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+ return ftmac110_initialize(bd);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_FTSDC010
+ return ftsdc010_mmc_init(0);
+#else
+ return 0;
+#endif
+}
diff --git a/board/faraday/a360evb/clock.c b/board/faraday/a360evb/clock.c
new file mode 100644
index 0000000..2bdba52
--- /dev/null
+++ b/board/faraday/a360evb/clock.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. <http://www.faraday-tech.com/tw/>
+ * Kuo-Jung Su <dantesu@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sysc.h>
+#include <faraday/ftpmu010.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct sysc_regs *sysc = (void __iomem *)CONFIG_SCU_BASE;
+static struct ftpmu010 *pmu = (void __iomem *)CONFIG_PMU_BASE;
+
+static inline ulong clk_get_rate_sys(void)
+{
+ return 40000000; /* 40 MHz */
+}
+
+static inline ulong clk_get_rate_ahb(void)
+{
+ return clk_get_rate_sys() * ((readl(&pmu->PDLLCR0) >> 3) & 0x3f) / 8;
+}
+
+static inline ulong clk_get_rate_apb(void)
+{
+ return clk_get_rate_ahb() >> 1;
+}
+
+static inline ulong clk_get_rate_cpu(void)
+{
+ uint32_t s = readl(&sysc->csr);
+ uint32_t p = readl(&pmu->PMODE);
+ ulong clk = clk_get_rate_ahb();
+ ulong mul = (s & CSR_PLL_PRESCALE) ? 2 : 4;
+
+ return (p & FTPMU010_PMODE_TURBO) ? (clk * mul) : clk;
+}
+
+ulong clk_get_rate(const char *id)
+{
+ ulong ret = 0;
+
+ if (!strcmp(id, "AHB"))
+ ret = clk_get_rate_ahb();
+ else if (!strcmp(id, "APB"))
+ ret = clk_get_rate_apb();
+ else if (!strcmp(id, "CPU"))
+ ret = clk_get_rate_cpu();
+ else if (!strcmp(id, "I2C"))
+ ret = clk_get_rate_apb();
+ else if (!strcmp(id, "MMC") || !strcmp(id, "SDC"))
+ ret = clk_get_rate_ahb();
+ else if (!strcmp(id, "SPI") || !strcmp(id, "SSP"))
+ ret = clk_get_rate_apb();
+
+ return ret;
+}
diff --git a/board/faraday/a360evb/lowlevel_init.S b/board/faraday/a360evb/lowlevel_init.S
new file mode 100644
index 0000000..cbc006d
--- /dev/null
+++ b/board/faraday/a360evb/lowlevel_init.S
@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. <http://www.faraday-tech.com/tw/>
+ * Kuo-Jung Su <dantesu@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+ mov pc,lr
diff --git a/boards.cfg b/boards.cfg
index c602a16..304417d 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -59,6 +59,7 @@ Active arm arm720t - armltd integrator
Active arm arm920t - armltd integrator integratorap_cm920t integratorap:CM920T Linus Walleij <linus.walleij@linaro.org>
Active arm arm920t - armltd integrator integratorcp_cm920t integratorcp:CM920T Linus Walleij <linus.walleij@linaro.org>
Active arm arm920t a320 faraday - a320evb - Po-Yu Chuang <ratbert@faraday-tech.com>
+Active arm faraday a360 faraday a360evb a360evb a360 Kuo-Jung Su <dantesu@gmail.com>
Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek at91rm9200ek Andreas Bie?mann <andreas.devel@gmail.com>
Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek_ram at91rm9200ek:RAMBOOT Andreas Bie?mann <andreas.devel@gmail.com>
Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2 eb_cpux9k2 Jens Scharsig <esw@bus-elektronik.de>
diff --git a/include/common.h b/include/common.h
index 44c6bab..5dd1ea1 100644
--- a/include/common.h
+++ b/include/common.h
@@ -94,6 +94,10 @@ typedef volatile unsigned char vu_char;
#ifdef CONFIG_SOC_DA8XX
#include <asm/arch/hardware.h>
#endif
+#ifdef CONFIG_SOC_FARADAY
+#include <asm/arch/hardware.h>
+#include <asm/faraday-common.h>
+#endif

#include <part.h>
#include <flash.h>
diff --git a/include/configs/a360.h b/include/configs/a360.h
new file mode 100644
index 0000000..91bb62a
--- /dev/null
+++ b/include/configs/a360.h
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. <http://www.faraday-tech.com/tw/>
+ * Kuo-Jung Su <dantesu@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+/* Memory Configuration */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_SIZE SZ_256M
+
+#define CONFIG_SYS_MALLOC_LEN SZ_2M
+#define CONFIG_SYS_TEXT_BASE 0x00800000
+
+/* Timer */
+#define CONFIG_FTTMR010
+
+/* Serial (UART) */
+#define CONFIG_FTUART010
+#define CONFIG_FTUART010_CLK 18432000
+#define CONFIG_BAUDRATE 38400
+
+/* NIC */
+#define CONFIG_FTMAC110
+
+/* I2C */
+#define CONFIG_FTI2C010
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+
+/* MMC/SD */
+#define CONFIG_FTSDC010
+
+/* USB */
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_USB_EHCI_BASE_LIST \
+ { CONFIG_FUSBH200_BASE, CONFIG_FOTG210_BASE }
+
+/* Environment */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE SZ_64K
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ /* Default network configuration */ \
+ "ethaddr=00:41:71:00:00:50\0" \
+ "serverip=10.0.0.128\0" \
+ "ipaddr=10.0.0.192\0"
+
+/* Faraday common configuration */
+#include "faraday-common.h"
+
+#endif /* EOF */
diff --git a/include/configs/faraday-common.h b/include/configs/faraday-common.h
new file mode 100644
index 0000000..caa6a1e
--- /dev/null
+++ b/include/configs/faraday-common.h
@@ -0,0 +1,253 @@
+/*
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. <http://www.faraday-tech.com/tw/>
+ * Kuo-Jung Su <dantesu@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_FARADAY_COMMON_H
+#define __CONFIG_FARADAY_COMMON_H
+
+/* Faraday SoC Platform */
+#define CONFIG_SOC_FARADAY
+#define CONFIG_MACH_TYPE 758 /* Faraday */
+
+/* Faraday ARMv5TE common configuration */
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+#define CONFIG_SYS_HZ 1000
+
+#ifdef CONFIG_SPL_BUILD
+# undef CONFIG_USE_IRQ
+# ifndef CONFIG_SYS_DCACHE_OFF
+# define CONFIG_SYS_DCACHE_OFF
+# endif
+#endif
+
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+# define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
+#endif
+
+#ifdef CONFIG_USE_IRQ
+# define CONFIG_STACKSIZE_IRQ SZ_32K
+# define CONFIG_STACKSIZE_FIQ SZ_32K
+#endif
+
+/*
+ * Initial stack pointer: GENERATED_GBL_DATA_SIZE in internal SRAM.
+ * Inside the board_init_f, the gd is first assigned to
+ * (CONFIG_SYS_INIT_SP_ADDR) & ~0x07) and then relocated to DRAM
+ * while calling relocate_code.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + SZ_4K - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN SZ_512K
+
+/* Default entry point */
+#ifndef CONFIG_SYS_UBOOT_START
+# define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#endif
+
+/* Default load address */
+#ifndef CONFIG_SYS_LOAD_ADDR
+# define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_8M)
+#endif
+
+/* U-Boot's built-in memory test */
+#ifndef CONFIG_SYS_MEMTEST_START
+# define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_8M)
+#endif
+
+#ifndef CONFIG_SYS_MEMTEST_END
+# define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + SZ_32M)
+#endif
+
+/*
+ * Serial driver
+ */
+#ifdef CONFIG_FTUART010
+# undef CONFIG_HWFLOW
+# undef CONFIG_MODEM_SUPPORT
+# define CONFIG_SYS_NS16550
+# define CONFIG_SYS_NS16550_SERIAL
+# ifdef CONFIG_FTUART010_CLK
+# define CONFIG_SYS_NS16550_CLK CONFIG_FTUART010_CLK
+# else
+# define CONFIG_SYS_NS16550_CLK 18432000
+# endif
+# define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_BASE
+# define CONFIG_SYS_NS16550_MEM32
+# define CONFIG_SYS_NS16550_REG_SIZE (-4)
+# define CONFIG_CONS_INDEX 1
+# ifndef CONFIG_BAUDRATE
+# define CONFIG_BAUDRATE 38400
+# endif
+#endif /* #ifdef CONFIG_FTUART010 */
+
+/*
+ * NIC driver
+ */
+#ifdef CONFIG_FTGMAC100
+# define CONFIG_FTGMAC100_EGIGA
+# define CONFIG_PHY_GIGE /* Enable giga phy support for miiphyutil.c */
+#endif
+
+#if defined(CONFIG_FTMAC110) || defined(CONFIG_FTGMAC100)
+# define CONFIG_PHY_MAX_ADDR 32
+# define CONFIG_RANDOM_MACADDR
+# define CONFIG_MII
+# define CONFIG_NET_MULTI
+# define CONFIG_NET_RETRY_COUNT 20
+# define CONFIG_DRIVER_ETHER
+# define CONFIG_CMD_MII
+# define CONFIG_CMD_PING
+#endif /* CONFIG_FTMAC110 || CONFIG_FTGMAC100 */
+
+/*
+ * I2C bus driver
+ */
+#ifdef CONFIG_FTI2C010
+# define CONFIG_SYS_I2C_FTI2C010
+#endif
+#ifdef CONFIG_SYS_I2C_FTI2C010
+# define CONFIG_SYS_I2C
+# define CONFIG_SYS_I2C_SPEED 5000
+# define CONFIG_SYS_I2C_SLAVE 0
+# define CONFIG_CMD_I2C
+# define CONFIG_I2C_CMD_TREE
+#endif /* CONFIG_FTI2C010 */
+
+/*
+ * I2C-EEPROM
+ */
+#ifdef CONFIG_ENV_EEPROM_IS_ON_I2C
+# define CONFIG_CMD_EEPROM
+# define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+# define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+# define CONFIG_SYS_I2C_MULTI_EEPROMS
+#endif
+
+/*
+ * NOR flash driver
+ */
+#ifdef CONFIG_SYS_FLASH_BASE
+# define CONFIG_SYS_FLASH_CFI
+# define CONFIG_FLASH_CFI_DRIVER
+# define CFG_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
+# define CONFIG_CMD_IMLS
+# define CONFIG_CMD_FLASH
+#else
+# define CONFIG_SYS_NO_FLASH
+#endif /* !CONFIG_SYS_NO_FLASH */
+
+/*
+ * MMC/SD
+ */
+#ifdef CONFIG_FTSDC010
+# define CONFIG_FTSDC010_SDIO /* HW is configured with SDIO support */
+#endif
+
+#ifdef CONFIG_FTSDC021
+# define CONFIG_SDHCI
+#endif
+
+#if defined(CONFIG_FTSDC010) || defined(CONFIG_FTSDC021)
+# define CONFIG_MMC
+# define CONFIG_CMD_MMC
+# define CONFIG_GENERIC_MMC
+#endif
+
+/*
+ * USB EHCI
+ */
+#if CONFIG_USB_MAX_CONTROLLER_COUNT > 0
+# define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
+# define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 500
+# define CONFIG_USB_EHCI
+# define CONFIG_USB_EHCI_FARADAY
+# define CONFIG_EHCI_IS_TDI
+# define CONFIG_CMD_USB
+# define CONFIG_USB_STORAGE
+#endif
+
+/*
+ * USB Gadget
+ */
+#ifdef CONFIG_USB_GADGET_FOTG210
+# define CONFIG_USB_GADGET
+# define CONFIG_USB_GADGET_DUALSPEED
+# define CONFIG_USB_ETHER
+# define CONFIG_USB_ETH_RNDIS
+# define CONFIG_USBNET_DEV_ADDR "00:41:71:00:00:55" /* U-Boot */
+# define CONFIG_USBNET_HOST_ADDR "00:41:71:00:00:54" /* Host PC */
+#endif
+
+/*
+ * U-Boot General Configurations
+ */
+#define CONFIG_LZMA /* Support LZMA */
+#define CONFIG_VERSION_VARIABLE /* Include version env variable */
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256
+
+/* Max number of command args */
+#define CONFIG_SYS_MAXARGS 32
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/*
+ * Shell
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "$ "
+#define CONFIG_SYS_PROMPT "=> "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * FAT Filesystem
+ */
+#if defined(CONFIG_USB_STORAGE) || defined(CONFIG_MMC)
+# define CONFIG_DOS_PARTITION
+# define CONFIG_CMD_FAT
+#endif
+
+/*
+ * Linux Kernel Command Line Options
+ */
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_TAG /* support ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+
+/*
+ * Default Commands
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMD_AUTOSCRIPT /* support autoscript */
+#define CONFIG_CMD_BDI /* bdinfo */
+#define CONFIG_CMD_ECHO /* echo arguments */
+#define CONFIG_CMD_ENV /* printenv */
+#define CONFIG_CMD_MEMORY /* md mm nm mw ... */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_RUN /* run command in env variable */
+#define CONFIG_CMD_ELF /* support ELF files */
+#define CONFIG_CMD_LOADB /* xyzModem */
+
+#ifndef CONFIG_ENV_IS_NOWHERE
+# define CONFIG_CMD_SAVEENV /* saveenv */
+#endif
+
+#endif /* EOF */
--
1.7.9.5