[U-Boot] [PATCH 2/9] mx23: regs-pinctrl.h: Add pinctrl support for mx23

Fabio Estevam
2013-05-01T21:44:42Z

From: Fabio Estevam <fabio.estevam@freescale.com>

Provide a mxs_pinctrl_regs structure for mx23.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
arch/arm/include/asm/arch-mxs/regs-pinctrl.h | 68 ++++++++++++++++++++++++++
1 file changed, 68 insertions(+)

diff --git a/arch/arm/include/asm/arch-mxs/regs-pinctrl.h b/arch/arm/include/asm/arch-mxs/regs-pinctrl.h
index c3a8700..fe7e910 100644
--- a/arch/arm/include/asm/arch-mxs/regs-pinctrl.h
+++ b/arch/arm/include/asm/arch-mxs/regs-pinctrl.h
@@ -29,6 +29,7 @@
#include <asm/imx-common/regs-common.h>

#ifndef __ASSEMBLY__
+#if defined(CONFIG_MX28)
struct mxs_pinctrl_regs {
mxs_reg_32(ctrl) /* 0x0 */

@@ -154,6 +155,73 @@ struct mxs_pinctrl_regs {

mxs_reg_32(emi_ds_ctrl) /* 0x1b80 */
};
+#elif defined(CONFIG_MX23)
+struct mxs_pinctrl_regs {
+ mxs_reg_32(ctrl) /* 0x0 */
+ int reserved1[0x3c];
+ mxs_reg_32(muxsel0) /* 0x100 */
+ mxs_reg_32(muxsel1) /* 0x110 */
+ mxs_reg_32(muxsel2) /* 0x120 */
+ mxs_reg_32(muxsel3) /* 0x130 */
+ mxs_reg_32(muxsel4) /* 0x140 */
+ mxs_reg_32(muxsel5) /* 0x150 */
+ mxs_reg_32(muxsel6) /* 0x160 */
+ mxs_reg_32(muxsel7) /* 0x170 */
+ int reserved2[0x20];
+ mxs_reg_32(drive0) /* 0x200 */
+ mxs_reg_32(drive1) /* 0x210 */
+ mxs_reg_32(drive2) /* 0x220 */
+ mxs_reg_32(drive3) /* 0x230 */
+ mxs_reg_32(drive4) /* 0x240 */
+ mxs_reg_32(drive5) /* 0x250 */
+ mxs_reg_32(drive6) /* 0x260 */
+ mxs_reg_32(drive7) /* 0x270 */
+ mxs_reg_32(drive8) /* 0x280 */
+ mxs_reg_32(drive9) /* 0x290 */
+ mxs_reg_32(drive10) /* 0x2a0 */
+ mxs_reg_32(drive11) /* 0x2b0 */
+ mxs_reg_32(drive12) /* 0x2c0 */
+ mxs_reg_32(drive13) /* 0x2d0 */
+ mxs_reg_32(drive14) /* 0x2e0 */
+ int reserved3[0x44];
+ mxs_reg_32(pull0) /* 0x400 */
+ mxs_reg_32(pull1) /* 0x410 */
+ mxs_reg_32(pull2) /* 0x420 */
+ mxs_reg_32(pull3) /* 0x430 */
+ int reserved4[0x30];
+ mxs_reg_32(dout0) /* 0x500 */
+ mxs_reg_32(dout1) /* 0x510 */
+ mxs_reg_32(dout2) /* 0x520 */
+ int reserved5[0x34];
+ mxs_reg_32(din0) /* 0x600 */
+ mxs_reg_32(din1) /* 0x610 */
+ mxs_reg_32(din2) /* 0x620 */
+ int reserved6[0x34];
+ mxs_reg_32(doe0) /* 0x700 */
+ mxs_reg_32(doe1) /* 0x710 */
+ mxs_reg_32(doe2) /* 0x720 */
+ int reserved7[0x34];
+ mxs_reg_32(pin2irq0) /* 0x800 */
+ mxs_reg_32(pin2irq1) /* 0x810 */
+ mxs_reg_32(pin2irq2) /* 0x820 */
+ int reserved8[0x34];
+ mxs_reg_32(irqen0) /* 0x900 */
+ mxs_reg_32(irqen1) /* 0x910 */
+ mxs_reg_32(irqen2) /* 0x920 */
+ int reserved9[0x34];
+ mxs_reg_32(irqlevel0) /* 0xa00 */
+ mxs_reg_32(irqlevel1) /* 0xa10 */
+ mxs_reg_32(irqlevel2) /* 0xa20 */
+ int reserved10[0x34];
+ mxs_reg_32(irqpol0) /* 0xb00 */
+ mxs_reg_32(irqpol1) /* 0xb10 */
+ mxs_reg_32(irqpol2) /* 0xb20 */
+ int reserved11[0x34];
+ mxs_reg_32(irqstat0) /* 0xc00 */
+ mxs_reg_32(irqstat1) /* 0xc10 */
+ mxs_reg_32(irqstat2) /* 0xc20 */
+};
+#endif
#endif

#define PINCTRL_CTRL_SFTRST (1 << 31)
--
1.7.9.5