[U-Boot] [PATCH 7/9] mxs: spl_mem_init: Remove unneeded DRAM configurations

[Fabio Estevam <festevam@gmail.com>]

From: Fabio Estevam <fabio.estevam@freescale.com>

There is no need to write to DRAM_CTL8 register prior to nitialize_dram_values().

Fix a comment related to writing to DRAM_CTL8.

Also, DRAM_CTL18 register on mx23 does not contain DRAM init complete bit, so
remove this setting as this is also not done by FSL bootlets code.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c |    9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index 1c509d6..cde883d 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -262,12 +262,9 @@ static void mx23_mem_init(void)
 	 * Configure the DRAM registers
 	 */
 
-	/* Clear START and SREFRESH bit from DRAM_CTL8 */
-	clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8));
-
 	initialize_dram_values();
 
-	/* Set START bit in DRAM_CTL16 */
+	/* Set START bit in DRAM_CTL8 */
 	setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
 
 	clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
@@ -279,10 +276,6 @@ static void mx23_mem_init(void)
 
 	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
 	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
-
-	/* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */
-	while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10)))
-		;
 }
 #endif
 
-- 
1.7.9.5