From mboxrd@z Thu Jan 1 00:00:00 1970 From: Fabio Estevam Date: Wed, 1 May 2013 18:44:48 -0300 Subject: [U-Boot] [PATCH 8/9] mxs: spl_mem_init: Skip the initialization of some DRAM_CTL registers In-Reply-To: <1367444689-31301-1-git-send-email-festevam@gmail.com> References: <1367444689-31301-1-git-send-email-festevam@gmail.com> Message-ID: <1367444689-31301-9-git-send-email-festevam@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Fabio Estevam HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as per FSL bootlets code. mx23 Reference Manual mark HW_DRAM_CTL27 and HW_DRAM_CTL28 as "reserved". HW_DRAM_CTL8 is setup as the last element. So skip the initialization of these DRAM_CTL registers. Signed-off-by: Fabio Estevam --- arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index cde883d..f500851 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -116,9 +116,12 @@ static void initialize_dram_values(void) mxs_adjust_memory_params(dram_vals); - for (i = 0; i < ARRAY_SIZE(dram_vals); i++) - writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); - + for (i = 0; i < ARRAY_SIZE(dram_vals); i++) { +#ifdef CONFIG_MX23 + if (!(i == 8 || i == 27 || i == 28 || i == 35)) +#endif + writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); + } #ifdef CONFIG_MX23 /* * Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last -- 1.7.9.5