From mboxrd@z Thu Jan 1 00:00:00 1970 From: Fabio Estevam Date: Fri, 3 May 2013 11:00:11 -0300 Subject: [U-Boot] [PATCH v4 5/7] mxs: spl_mem_init: Remove erroneous DDR setting In-Reply-To: <1367589613-18065-1-git-send-email-festevam@gmail.com> References: <1367589613-18065-1-git-send-email-festevam@gmail.com> Message-ID: <1367589613-18065-6-git-send-email-festevam@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Fabio Estevam On mx23 there is no 'DRAM init complete' in register HW_DRAM_CTL18. Remove this erroneous setting. Signed-off-by: Fabio Estevam --- Changes since v3: - None Changes since v2: - None Changes since v1: - Newly introduced as the previous patch is now splitted. arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index 300da0a..df25535 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -279,10 +279,6 @@ static void mx23_mem_init(void) setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19); setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11); - - /* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */ - while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10))) - ; } #endif -- 1.7.9.5