From mboxrd@z Thu Jan 1 00:00:00 1970 From: Henrik =?ISO-8859-1?Q?Nordstr=F6m?= Date: Thu, 16 May 2013 03:54:38 +0200 Subject: [U-Boot] ARM v7: Flush icache when executing a program with go In-Reply-To: <20130515193959.69aa9d64@lilith> References: <1368540962.4464.9.camel@localhost> <20130515171111.481eb3de@lilith> <1368635647.3991.18.camel@localhost> <20130515184410.26e34874@lilith> <20130515165121.GG29196@bill-the-cat> <20130515193959.69aa9d64@lilith> Message-ID: <1368669278.27007.43.camel@localhost> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de ons 2013-05-15 klockan 19:39 +0200 skrev Albert ARIBAUD: > I understand all this, but what I am interested in is the root issue. > > IIUC, the problem is that some code is loaded in DDR, and the CPU is > about to jump to it, but its instruction cache is enabled so maybe some > instructions after 'go' will be (wrongly) fetched from I-cache instead > of being read from DDR (and fed into I-cache). Yes. > Nothing in this is ARMv7 specific; it could happen in an arm926ejs just > as well. It could happen on any CPU with distinct, non-consistent I- > and D- caches an enabled I-cache. Correct on all accounts. > So my suggestion is to implement the icache_flush in common/bmmt_cmd.c > as follows: > > ... > /* just about to 'go' */ > #if CONFIG_ARM > #if CONFIG_ICACHE > if (icache_status()) > invalidate_icache_all(); > #endif /* CONFIG_ICACHE */ > #endif /* CONFIG_ARM */ > /* now go */ This style is a nightmare for adding more arches needing this, but solves the problem today. But there is no CONFIG_ICACHE. In ARM there is CONFIG_SYS_ICACHE_OFF but it's not quite the same.