* [U-Boot] [PATCH 1/1] socfpga: Adding System Manager driver which will configure the pin mux for real hardware Cyclone V
[not found] ` <0BB3B561D7068A4E89FD8E9ABFB538BEB3B2E44332@PG-ITMSG03.altera.priv.altera.com>
@ 2013-06-27 13:35 ` Chin Liang See
2013-06-28 11:40 ` Pavel Machek
0 siblings, 1 reply; 12+ messages in thread
From: Chin Liang See @ 2013-06-27 13:35 UTC (permalink / raw)
To: u-boot
socfpga: Adding System Manager driver which will configure the pin mux
for real hardware Cyclone V development kit (not Virtual Platform)
Signed-off-by: Chin Liang See <clsee@altera.com>
---
arch/arm/cpu/armv7/socfpga/Makefile | 2 +-
arch/arm/cpu/armv7/socfpga/spl.c | 6 +
arch/arm/cpu/armv7/socfpga/system_manager.c | 40 ++++
.../include/asm/arch-socfpga/socfpga_base_addrs.h | 1 +
arch/arm/include/asm/arch-socfpga/system_manager.h | 32 +++
board/altera/socfpga_cyclone5/Makefile | 4 +-
board/altera/socfpga_cyclone5/pinmux_config.c | 213 ++++++++++++++++++++
board/altera/socfpga_cyclone5/pinmux_config.h | 53 +++++
include/configs/socfpga_cyclone5.h | 1 +
9 files changed, 350 insertions(+), 2 deletions(-) create mode
100644 arch/arm/cpu/armv7/socfpga/system_manager.c
create mode 100644 arch/arm/include/asm/arch-socfpga/system_manager.h
create mode 100644 board/altera/socfpga_cyclone5/pinmux_config.c
create mode 100644 board/altera/socfpga_cyclone5/pinmux_config.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index 518e67a..cf2829a 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
-COBJS-y := misc.o timer.o reset_manager.o
+COBJS-y := misc.o timer.o reset_manager.o system_manager.o
COBJS-$(CONFIG_SPL_BUILD) += spl.o
COBJS := $(COBJS-y)
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index 84216eb..28d8c99 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -23,6 +23,7 @@
#include <image.h>
#include <asm/arch/reset_manager.h>
#include <spl.h>
+#include <asm/arch/system_manager.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -36,6 +37,11 @@ u32 spl_boot_device(void)
*/
void spl_board_init(void)
{
+#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
+ /* configure the pin muxing through system manager */
+ sysmgr_pinmux_init();
+#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
+
/* de-assert reset for peripherals and bridges based on handoff */
reset_deassert_peripherals_handoff();
diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c
b/arch/arm/cpu/armv7/socfpga/system_manager.c
new file mode 100644
index 0000000..f2707d8b
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/system_manager.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright Altera Corporation (C) 2013. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or
+modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but
+WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+along
+ * with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/system_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Configure all the pin mux
+ */
+void sysmgr_pinmux_init(void)
+{
+ unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET;
+
+ const unsigned long *pval = sys_mgr_init_table;
+ unsigned long i;
+
+ for (i = 0;
+ i < ((sizeof(sys_mgr_init_table)) / sizeof(unsigned long));
+ i++, offset += sizeof(unsigned long)) {
+ writel(*pval++, (SOCFPGA_SYSMGR_ADDRESS + offset));
+ }
+}
+
+
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
index f353eb2..819c280 100644
--- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
+++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
@@ -23,5 +23,6 @@
#define SOCFPGA_UART1_ADDRESS 0xffc03000 #define
SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 #define SOCFPGA_RSTMGR_ADDRESS
0xffd05000
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
#endif /* _SOCFPGA_BASE_ADDRS_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h
b/arch/arm/include/asm/arch-socfpga/system_manager.h
new file mode 100644
index 0000000..aec9be7
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/system_manager.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright Altera Corporation (C) 2013. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or
+modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but
+WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+along
+ * with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SYSTEM_MANAGER_H_
+#define _SYSTEM_MANAGER_H_
+
+#ifndef __ASSEMBLY__
+
+void sysmgr_pinmux_init(void);
+
+/* declaration for handoff table type */ extern unsigned long
+sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM];
+
+#endif
+
+
+#define CONFIG_SYSMGR_PINMUXGRP_OFFSET (0x400)
+
+#endif /* _SYSTEM_MANAGER_H_ */
diff --git a/board/altera/socfpga_cyclone5/Makefile
b/board/altera/socfpga_cyclone5/Makefile
index 43bbc37..3092387 100644
--- a/board/altera/socfpga_cyclone5/Makefile
+++ b/board/altera/socfpga_cyclone5/Makefile
@@ -26,8 +26,10 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
-COBJS := socfpga_cyclone5.o
+COBJS-y := socfpga_cyclone5.o
+COBJS-$(CONFIG_SPL_BUILD) += pinmux_config.o
+COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/altera/socfpga_cyclone5/pinmux_config.c
b/board/altera/socfpga_cyclone5/pinmux_config.c
new file mode 100644
index 0000000..42e7c89
--- /dev/null
+++ b/board/altera/socfpga_cyclone5/pinmux_config.c
@@ -0,0 +1,213 @@
+
+#include "pinmux_config.h"
+
+/* pin mux configuration data */
+unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
+ 0, /* EMACIO0 - Unused */
+ 2, /* EMACIO1 - USB */
+ 2, /* EMACIO2 - USB */
+ 2, /* EMACIO3 - USB */
+ 2, /* EMACIO4 - USB */
+ 2, /* EMACIO5 - USB */
+ 2, /* EMACIO6 - USB */
+ 2, /* EMACIO7 - USB */
+ 2, /* EMACIO8 - USB */
+ 0, /* EMACIO9 - Unused */
+ 2, /* EMACIO10 - USB */
+ 2, /* EMACIO11 - USB */
+ 2, /* EMACIO12 - USB */
+ 2, /* EMACIO13 - USB */
+ 0, /* EMACIO14 - N/A */
+ 0, /* EMACIO15 - N/A */
+ 0, /* EMACIO16 - N/A */
+ 0, /* EMACIO17 - N/A */
+ 0, /* EMACIO18 - N/A */
+ 0, /* EMACIO19 - N/A */
+ 3, /* FLASHIO0 - SDMMC */
+ 3, /* FLASHIO1 - SDMMC */
+ 3, /* FLASHIO2 - SDMMC */
+ 3, /* FLASHIO3 - SDMMC */
+ 0, /* FLASHIO4 - SDMMC */
+ 0, /* FLASHIO5 - SDMMC */
+ 0, /* FLASHIO6 - SDMMC */
+ 0, /* FLASHIO7 - SDMMC */
+ 0, /* FLASHIO8 - SDMMC */
+ 3, /* FLASHIO9 - SDMMC */
+ 3, /* FLASHIO10 - SDMMC */
+ 3, /* FLASHIO11 - SDMMC */
+ 3, /* GENERALIO0 - TRACE */
+ 3, /* GENERALIO1 - TRACE */
+ 3, /* GENERALIO2 - TRACE */
+ 3, /* GENERALIO3 - TRACE */
+ 3, /* GENERALIO4 - TRACE */
+ 3, /* GENERALIO5 - TRACE */
+ 3, /* GENERALIO6 - TRACE */
+ 3, /* GENERALIO7 - TRACE */
+ 3, /* GENERALIO8 - TRACE */
+ 3, /* GENERALIO9 - SPIM0 */
+ 3, /* GENERALIO10 - SPIM0 */
+ 3, /* GENERALIO11 - SPIM0 */
+ 3, /* GENERALIO12 - SPIM0 */
+ 2, /* GENERALIO13 - CAN0 */
+ 2, /* GENERALIO14 - CAN0 */
+ 3, /* GENERALIO15 - I2C0 */
+ 3, /* GENERALIO16 - I2C0 */
+ 2, /* GENERALIO17 - UART0 */
+ 2, /* GENERALIO18 - UART0 */
+ 0, /* GENERALIO19 - N/A */
+ 0, /* GENERALIO20 - N/A */
+ 0, /* GENERALIO21 - N/A */
+ 0, /* GENERALIO22 - N/A */
+ 0, /* GENERALIO23 - N/A */
+ 0, /* GENERALIO24 - N/A */
+ 0, /* GENERALIO25 - N/A */
+ 0, /* GENERALIO26 - N/A */
+ 0, /* GENERALIO27 - N/A */
+ 0, /* GENERALIO28 - N/A */
+ 0, /* GENERALIO29 - N/A */
+ 0, /* GENERALIO30 - N/A */
+ 0, /* GENERALIO31 - N/A */
+ 2, /* MIXED1IO0 - EMAC */
+ 2, /* MIXED1IO1 - EMAC */
+ 2, /* MIXED1IO2 - EMAC */
+ 2, /* MIXED1IO3 - EMAC */
+ 2, /* MIXED1IO4 - EMAC */
+ 2, /* MIXED1IO5 - EMAC */
+ 2, /* MIXED1IO6 - EMAC */
+ 2, /* MIXED1IO7 - EMAC */
+ 2, /* MIXED1IO8 - EMAC */
+ 2, /* MIXED1IO9 - EMAC */
+ 2, /* MIXED1IO10 - EMAC */
+ 2, /* MIXED1IO11 - EMAC */
+ 2, /* MIXED1IO12 - EMAC */
+ 2, /* MIXED1IO13 - EMAC */
+ 0, /* MIXED1IO14 - Unused */
+ 3, /* MIXED1IO15 - QSPI */
+ 3, /* MIXED1IO16 - QSPI */
+ 3, /* MIXED1IO17 - QSPI */
+ 3, /* MIXED1IO18 - QSPI */
+ 3, /* MIXED1IO19 - QSPI */
+ 3, /* MIXED1IO20 - QSPI */
+ 0, /* MIXED1IO21 - GPIO */
+ 0, /* MIXED2IO0 - N/A */
+ 0, /* MIXED2IO1 - N/A */
+ 0, /* MIXED2IO2 - N/A */
+ 0, /* MIXED2IO3 - N/A */
+ 0, /* MIXED2IO4 - N/A */
+ 0, /* MIXED2IO5 - N/A */
+ 0, /* MIXED2IO6 - N/A */
+ 0, /* MIXED2IO7 - N/A */
+ 0, /* GPLINMUX48 */
+ 0, /* GPLINMUX49 */
+ 0, /* GPLINMUX50 */
+ 0, /* GPLINMUX51 */
+ 0, /* GPLINMUX52 */
+ 0, /* GPLINMUX53 */
+ 0, /* GPLINMUX54 */
+ 0, /* GPLINMUX55 */
+ 0, /* GPLINMUX56 */
+ 0, /* GPLINMUX57 */
+ 0, /* GPLINMUX58 */
+ 0, /* GPLINMUX59 */
+ 0, /* GPLINMUX60 */
+ 0, /* GPLINMUX61 */
+ 0, /* GPLINMUX62 */
+ 0, /* GPLINMUX63 */
+ 0, /* GPLINMUX64 */
+ 0, /* GPLINMUX65 */
+ 0, /* GPLINMUX66 */
+ 0, /* GPLINMUX67 */
+ 0, /* GPLINMUX68 */
+ 0, /* GPLINMUX69 */
+ 0, /* GPLINMUX70 */
+ 1, /* GPLMUX0 */
+ 1, /* GPLMUX1 */
+ 1, /* GPLMUX2 */
+ 1, /* GPLMUX3 */
+ 1, /* GPLMUX4 */
+ 1, /* GPLMUX5 */
+ 1, /* GPLMUX6 */
+ 1, /* GPLMUX7 */
+ 1, /* GPLMUX8 */
+ 1, /* GPLMUX9 */
+ 1, /* GPLMUX10 */
+ 1, /* GPLMUX11 */
+ 1, /* GPLMUX12 */
+ 1, /* GPLMUX13 */
+ 1, /* GPLMUX14 */
+ 1, /* GPLMUX15 */
+ 1, /* GPLMUX16 */
+ 1, /* GPLMUX17 */
+ 1, /* GPLMUX18 */
+ 1, /* GPLMUX19 */
+ 1, /* GPLMUX20 */
+ 1, /* GPLMUX21 */
+ 1, /* GPLMUX22 */
+ 1, /* GPLMUX23 */
+ 1, /* GPLMUX24 */
+ 1, /* GPLMUX25 */
+ 1, /* GPLMUX26 */
+ 1, /* GPLMUX27 */
+ 1, /* GPLMUX28 */
+ 1, /* GPLMUX29 */
+ 1, /* GPLMUX30 */
+ 1, /* GPLMUX31 */
+ 1, /* GPLMUX32 */
+ 1, /* GPLMUX33 */
+ 1, /* GPLMUX34 */
+ 1, /* GPLMUX35 */
+ 1, /* GPLMUX36 */
+ 1, /* GPLMUX37 */
+ 1, /* GPLMUX38 */
+ 1, /* GPLMUX39 */
+ 1, /* GPLMUX40 */
+ 1, /* GPLMUX41 */
+ 1, /* GPLMUX42 */
+ 1, /* GPLMUX43 */
+ 1, /* GPLMUX44 */
+ 1, /* GPLMUX45 */
+ 1, /* GPLMUX46 */
+ 1, /* GPLMUX47 */
+ 1, /* GPLMUX48 */
+ 1, /* GPLMUX49 */
+ 1, /* GPLMUX50 */
+ 1, /* GPLMUX51 */
+ 1, /* GPLMUX52 */
+ 1, /* GPLMUX53 */
+ 1, /* GPLMUX54 */
+ 1, /* GPLMUX55 */
+ 1, /* GPLMUX56 */
+ 1, /* GPLMUX57 */
+ 1, /* GPLMUX58 */
+ 1, /* GPLMUX59 */
+ 1, /* GPLMUX60 */
+ 1, /* GPLMUX61 */
+ 1, /* GPLMUX62 */
+ 1, /* GPLMUX63 */
+ 1, /* GPLMUX64 */
+ 1, /* GPLMUX65 */
+ 1, /* GPLMUX66 */
+ 1, /* GPLMUX67 */
+ 1, /* GPLMUX68 */
+ 1, /* GPLMUX69 */
+ 1, /* GPLMUX70 */
+ 0, /* NANDUSEFPGA */
+ 0, /* UART0USEFPGA */
+ 0, /* RGMII1USEFPGA */
+ 0, /* SPIS0USEFPGA */
+ 0, /* CAN0USEFPGA */
+ 0, /* I2C0USEFPGA */
+ 0, /* SDMMCUSEFPGA */
+ 0, /* QSPIUSEFPGA */
+ 0, /* SPIS1USEFPGA */
+ 0, /* RGMII0USEFPGA */
+ 0, /* UART1USEFPGA */
+ 0, /* CAN1USEFPGA */
+ 0, /* USB1USEFPGA */
+ 0, /* I2C3USEFPGA */
+ 0, /* I2C2USEFPGA */
+ 0, /* I2C1USEFPGA */
+ 0, /* SPIM1USEFPGA */
+ 0, /* USB0USEFPGA */
+ 0 /* SPIM0USEFPGA */
+};
diff --git a/board/altera/socfpga_cyclone5/pinmux_config.h
b/board/altera/socfpga_cyclone5/pinmux_config.h
new file mode 100644
index 0000000..33628c8
--- /dev/null
+++ b/board/altera/socfpga_cyclone5/pinmux_config.h
@@ -0,0 +1,53 @@
+
+#ifndef _PRELOADER_PINMUX_CONFIG_H_
+#define _PRELOADER_PINMUX_CONFIG_H_
+
+/*
+ * State of enabling for which IP connected out through the muxing.
+ * Value 1 mean the IP connection is muxed out */
+#define CONFIG_HPS_EMAC0 (0)
+#define CONFIG_HPS_EMAC1 (1)
+#define CONFIG_HPS_USB0 (0)
+#define CONFIG_HPS_USB1 (1)
+#define CONFIG_HPS_NAND (0)
+#define CONFIG_HPS_SDMMC (1)
+#define CONFIG_HPS_QSPI (1)
+#define CONFIG_HPS_UART0 (1)
+#define CONFIG_HPS_UART1 (0)
+#define CONFIG_HPS_TRACE (1)
+#define CONFIG_HPS_I2C0 (1)
+#define CONFIG_HPS_I2C1 (0)
+#define CONFIG_HPS_I2C2 (0)
+#define CONFIG_HPS_I2C3 (0)
+#define CONFIG_HPS_SPIM0 (1)
+#define CONFIG_HPS_SPIM1 (0)
+#define CONFIG_HPS_SPIS0 (0)
+#define CONFIG_HPS_SPIS1 (0)
+#define CONFIG_HPS_CAN0 (1)
+#define CONFIG_HPS_CAN1 (0)
+
+/* IP attribute value (which affected by pin muxing configuration) */
+#define CONFIG_HPS_SDMMC_BUSWIDTH (4)
+
+/* 1 if the pins are connected out */
+#define CONFIG_HPS_QSPI_CS0 (1)
+#define CONFIG_HPS_QSPI_CS1 (0)
+#define CONFIG_HPS_QSPI_CS2 (0)
+#define CONFIG_HPS_QSPI_CS3 (0)
+
+/* UART */
+/* 1 means the pin is mux out or available */
+#define CONFIG_HPS_UART0_TX (1)
+#define CONFIG_HPS_UART0_RX (1)
+#define CONFIG_HPS_UART0_CTS (0)
+#define CONFIG_HPS_UART0_RTS (0)
+#define CONFIG_HPS_UART1_TX (0)
+#define CONFIG_HPS_UART1_RX (0)
+#define CONFIG_HPS_UART1_CTS (0)
+#define CONFIG_HPS_UART1_RTS (0)
+
+/* Pin mux data */
+#define CONFIG_HPS_PINMUX_NUM (207)
+
+#endif /* _PRELOADER_PINMUX_CONFIG_H_ */
diff --git a/include/configs/socfpga_cyclone5.h
b/include/configs/socfpga_cyclone5.h
index 86563b7..02c5448 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -18,6 +18,7 @@
#define __CONFIG_H
#include <asm/arch/socfpga_base_addrs.h>
+#include "../../board/altera/socfpga_cyclone5/pinmux_config.h"
/*
* High level configuration
--
1.7.7.4
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 1/1] socfpga: Adding System Manager driver which will configure the pin mux for real hardware Cyclone V
2013-06-27 13:35 ` [U-Boot] [PATCH 1/1] socfpga: Adding System Manager driver which will configure the pin mux for real hardware Cyclone V Chin Liang See
@ 2013-06-28 11:40 ` Pavel Machek
2013-06-28 16:10 ` Chin Liang See
2013-06-28 21:20 ` [U-Boot] [PATCH v2 " Chin Liang See
0 siblings, 2 replies; 12+ messages in thread
From: Pavel Machek @ 2013-06-28 11:40 UTC (permalink / raw)
To: u-boot
Hi!
> socfpga: Adding System Manager driver which will configure the pin mux
> for real hardware Cyclone V development kit (not Virtual Platform)
>
> Signed-off-by: Chin Liang See <clsee@altera.com>
> diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c
> b/arch/arm/cpu/armv7/socfpga/system_manager.c
> new file mode 100644
> index 0000000..f2707d8b
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/socfpga/system_manager.c
> @@ -0,0 +1,40 @@
> +/*
> + * Copyright Altera Corporation (C) 2013. All rights reserved
> + *
> + * This program is free software; you can redistribute it and/or
> +modify it
Word wrapped.
> +/*
> + * Configure all the pin mux
> + */
"the pin muxes" ?
> +void sysmgr_pinmux_init(void)
> +{
> + unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET;
> +
> + const unsigned long *pval = sys_mgr_init_table;
> + unsigned long i;
> +
> + for (i = 0;
> + i < ((sizeof(sys_mgr_init_table)) / sizeof(unsigned long));
There's nice ARRAY_SIZE() macro that can be used.
> --- /dev/null
> +++ b/board/altera/socfpga_cyclone5/pinmux_config.c
> @@ -0,0 +1,213 @@
> +
> +#include "pinmux_config.h"
> +
> +/* pin mux configuration data */
> +unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
> + 0, /* EMACIO0 - Unused */
> + 2, /* EMACIO1 - USB */
> + 2, /* EMACIO2 - USB */
> + 2, /* EMACIO3 - USB */
Is this table auto-generated somehow?
If so, comment about that would be nice.
If not, perhaps we could put more than one entry on line, to make it
shorter?
Thanks,
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 1/1] socfpga: Adding System Manager driver which will configure the pin mux for real hardware Cyclone V
2013-06-28 11:40 ` Pavel Machek
@ 2013-06-28 16:10 ` Chin Liang See
2013-07-01 10:39 ` Pavel Machek
2013-06-28 21:20 ` [U-Boot] [PATCH v2 " Chin Liang See
1 sibling, 1 reply; 12+ messages in thread
From: Chin Liang See @ 2013-06-28 16:10 UTC (permalink / raw)
To: u-boot
Hi Pavel,
On Fri, 2013-06-28 at 13:40 +0200, ZY - pavel wrote:
> Hi!
>
> > socfpga: Adding System Manager driver which will configure the pin mux
> > for real hardware Cyclone V development kit (not Virtual Platform)
> >
> > Signed-off-by: Chin Liang See <clsee@altera.com>
>
> > diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c
> > b/arch/arm/cpu/armv7/socfpga/system_manager.c
> > new file mode 100644
> > index 0000000..f2707d8b
> > --- /dev/null
> > +++ b/arch/arm/cpu/armv7/socfpga/system_manager.c
> > @@ -0,0 +1,40 @@
> > +/*
> > + * Copyright Altera Corporation (C) 2013. All rights reserved
> > + *
> > + * This program is free software; you can redistribute it and/or
> > +modify it
>
> Word wrapped.
Will fix with new email client
>
> > +/*
> > + * Configure all the pin mux
> > + */
>
> "the pin muxes" ?
Noted
>
> > +void sysmgr_pinmux_init(void)
> > +{
> > + unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET;
> > +
> > + const unsigned long *pval = sys_mgr_init_table;
> > + unsigned long i;
> > +
> > + for (i = 0;
> > + i < ((sizeof(sys_mgr_init_table)) / sizeof(unsigned long));
>
> There's nice ARRAY_SIZE() macro that can be used.
>
Noted
>
> > --- /dev/null
> > +++ b/board/altera/socfpga_cyclone5/pinmux_config.c
> > @@ -0,0 +1,213 @@
> > +
> > +#include "pinmux_config.h"
> > +
> > +/* pin mux configuration data */
> > +unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
> > + 0, /* EMACIO0 - Unused */
> > + 2, /* EMACIO1 - USB */
> > + 2, /* EMACIO2 - USB */
> > + 2, /* EMACIO3 - USB */
>
> Is this table auto-generated somehow?
>
> If so, comment about that would be nice.
>
> If not, perhaps we could put more than one entry on line, to make it
> shorter?
Yup, its auto generated by tools.
I will put comment to note this.
Thanks
Chin Liang
>
> Thanks,
> Pavel
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH v2 1/1] socfpga: Adding System Manager driver which will configure the pin mux for real hardware Cyclone V
2013-06-28 11:40 ` Pavel Machek
2013-06-28 16:10 ` Chin Liang See
@ 2013-06-28 21:20 ` Chin Liang See
2013-06-28 22:52 ` Wolfgang Denk
2013-07-01 10:42 ` Pavel Machek
1 sibling, 2 replies; 12+ messages in thread
From: Chin Liang See @ 2013-06-28 21:20 UTC (permalink / raw)
To: u-boot
socfpga: Adding System Manager driver which will
configure the pin mux for real hardware Cyclone V
development kit (not Virtual Platform)
Signed-off-by: Chin Liang See <clsee@altera.com>
---
arch/arm/cpu/armv7/socfpga/Makefile | 2 +-
arch/arm/cpu/armv7/socfpga/spl.c | 6 +
arch/arm/cpu/armv7/socfpga/system_manager.c | 41 ++++
.../include/asm/arch-socfpga/socfpga_base_addrs.h | 1 +
arch/arm/include/asm/arch-socfpga/system_manager.h | 34 ++++
board/altera/socfpga_cyclone5/Makefile | 4 +-
board/altera/socfpga_cyclone5/pinmux_config.c | 214
++++++++++++++++++++
board/altera/socfpga_cyclone5/pinmux_config.h | 54 +++++
include/configs/socfpga_cyclone5.h | 1 +
9 files changed, 355 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/system_manager.c
create mode 100644 arch/arm/include/asm/arch-socfpga/system_manager.h
create mode 100644 board/altera/socfpga_cyclone5/pinmux_config.c
create mode 100644 board/altera/socfpga_cyclone5/pinmux_config.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index 518e67a..cf2829a 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
-COBJS-y := misc.o timer.o reset_manager.o
+COBJS-y := misc.o timer.o reset_manager.o system_manager.o
COBJS-$(CONFIG_SPL_BUILD) += spl.o
COBJS := $(COBJS-y)
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c
b/arch/arm/cpu/armv7/socfpga/spl.c
index 84216eb..28d8c99 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -23,6 +23,7 @@
#include <image.h>
#include <asm/arch/reset_manager.h>
#include <spl.h>
+#include <asm/arch/system_manager.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -36,6 +37,11 @@ u32 spl_boot_device(void)
*/
void spl_board_init(void)
{
+#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
+ /* configure the pin muxing through system manager */
+ sysmgr_pinmux_init();
+#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
+
/* de-assert reset for peripherals and bridges based on handoff */
reset_deassert_peripherals_handoff();
diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c
b/arch/arm/cpu/armv7/socfpga/system_manager.c
new file mode 100644
index 0000000..ef5f49e
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/system_manager.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright Altera Corporation (C) 2013. All rights reserved
+ *
+ * This program is free software; you can redistribute it
+ * and/or modify it under the terms and conditions of the
+ * GNU General Public License, version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program. If not, see
+ * <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/system_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Configure all the pin mux
+ */
+void sysmgr_pinmux_init(void)
+{
+ unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET;
+
+ const unsigned long *pval = sys_mgr_init_table;
+ unsigned long i;
+
+ for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table);
+ i++, offset += sizeof(unsigned long)) {
+ writel(*pval++, (SOCFPGA_SYSMGR_ADDRESS + offset));
+ }
+}
+
+
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
index f353eb2..819c280 100644
--- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
+++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
@@ -23,5 +23,6 @@
#define SOCFPGA_UART1_ADDRESS 0xffc03000
#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
#endif /* _SOCFPGA_BASE_ADDRS_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h
b/arch/arm/include/asm/arch-socfpga/system_manager.h
new file mode 100644
index 0000000..ef9e464
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/system_manager.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright Altera Corporation (C) 2013. All rights reserved
+ *
+ * This program is free software; you can redistribute it
+ * and/or modify it under the terms and conditions of the
+ * GNU General Public License, version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program. If not, see
+ * <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SYSTEM_MANAGER_H_
+#define _SYSTEM_MANAGER_H_
+
+#ifndef __ASSEMBLY__
+
+void sysmgr_pinmux_init(void);
+
+/* declaration for handoff table type */
+extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM];
+
+#endif
+
+
+#define CONFIG_SYSMGR_PINMUXGRP_OFFSET (0x400)
+
+#endif /* _SYSTEM_MANAGER_H_ */
diff --git a/board/altera/socfpga_cyclone5/Makefile
b/board/altera/socfpga_cyclone5/Makefile
index 43bbc37..3092387 100644
--- a/board/altera/socfpga_cyclone5/Makefile
+++ b/board/altera/socfpga_cyclone5/Makefile
@@ -26,8 +26,10 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
-COBJS := socfpga_cyclone5.o
+COBJS-y := socfpga_cyclone5.o
+COBJS-$(CONFIG_SPL_BUILD) += pinmux_config.o
+COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/altera/socfpga_cyclone5/pinmux_config.c
b/board/altera/socfpga_cyclone5/pinmux_config.c
new file mode 100644
index 0000000..8b09005
--- /dev/null
+++ b/board/altera/socfpga_cyclone5/pinmux_config.c
@@ -0,0 +1,214 @@
+/* This file is generated by Preloader Generator */
+
+#include "pinmux_config.h"
+
+/* pin mux configuration data */
+unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
+ 0, /* EMACIO0 - Unused */
+ 2, /* EMACIO1 - USB */
+ 2, /* EMACIO2 - USB */
+ 2, /* EMACIO3 - USB */
+ 2, /* EMACIO4 - USB */
+ 2, /* EMACIO5 - USB */
+ 2, /* EMACIO6 - USB */
+ 2, /* EMACIO7 - USB */
+ 2, /* EMACIO8 - USB */
+ 0, /* EMACIO9 - Unused */
+ 2, /* EMACIO10 - USB */
+ 2, /* EMACIO11 - USB */
+ 2, /* EMACIO12 - USB */
+ 2, /* EMACIO13 - USB */
+ 0, /* EMACIO14 - N/A */
+ 0, /* EMACIO15 - N/A */
+ 0, /* EMACIO16 - N/A */
+ 0, /* EMACIO17 - N/A */
+ 0, /* EMACIO18 - N/A */
+ 0, /* EMACIO19 - N/A */
+ 3, /* FLASHIO0 - SDMMC */
+ 3, /* FLASHIO1 - SDMMC */
+ 3, /* FLASHIO2 - SDMMC */
+ 3, /* FLASHIO3 - SDMMC */
+ 0, /* FLASHIO4 - SDMMC */
+ 0, /* FLASHIO5 - SDMMC */
+ 0, /* FLASHIO6 - SDMMC */
+ 0, /* FLASHIO7 - SDMMC */
+ 0, /* FLASHIO8 - SDMMC */
+ 3, /* FLASHIO9 - SDMMC */
+ 3, /* FLASHIO10 - SDMMC */
+ 3, /* FLASHIO11 - SDMMC */
+ 3, /* GENERALIO0 - TRACE */
+ 3, /* GENERALIO1 - TRACE */
+ 3, /* GENERALIO2 - TRACE */
+ 3, /* GENERALIO3 - TRACE */
+ 3, /* GENERALIO4 - TRACE */
+ 3, /* GENERALIO5 - TRACE */
+ 3, /* GENERALIO6 - TRACE */
+ 3, /* GENERALIO7 - TRACE */
+ 3, /* GENERALIO8 - TRACE */
+ 3, /* GENERALIO9 - SPIM0 */
+ 3, /* GENERALIO10 - SPIM0 */
+ 3, /* GENERALIO11 - SPIM0 */
+ 3, /* GENERALIO12 - SPIM0 */
+ 2, /* GENERALIO13 - CAN0 */
+ 2, /* GENERALIO14 - CAN0 */
+ 3, /* GENERALIO15 - I2C0 */
+ 3, /* GENERALIO16 - I2C0 */
+ 2, /* GENERALIO17 - UART0 */
+ 2, /* GENERALIO18 - UART0 */
+ 0, /* GENERALIO19 - N/A */
+ 0, /* GENERALIO20 - N/A */
+ 0, /* GENERALIO21 - N/A */
+ 0, /* GENERALIO22 - N/A */
+ 0, /* GENERALIO23 - N/A */
+ 0, /* GENERALIO24 - N/A */
+ 0, /* GENERALIO25 - N/A */
+ 0, /* GENERALIO26 - N/A */
+ 0, /* GENERALIO27 - N/A */
+ 0, /* GENERALIO28 - N/A */
+ 0, /* GENERALIO29 - N/A */
+ 0, /* GENERALIO30 - N/A */
+ 0, /* GENERALIO31 - N/A */
+ 2, /* MIXED1IO0 - EMAC */
+ 2, /* MIXED1IO1 - EMAC */
+ 2, /* MIXED1IO2 - EMAC */
+ 2, /* MIXED1IO3 - EMAC */
+ 2, /* MIXED1IO4 - EMAC */
+ 2, /* MIXED1IO5 - EMAC */
+ 2, /* MIXED1IO6 - EMAC */
+ 2, /* MIXED1IO7 - EMAC */
+ 2, /* MIXED1IO8 - EMAC */
+ 2, /* MIXED1IO9 - EMAC */
+ 2, /* MIXED1IO10 - EMAC */
+ 2, /* MIXED1IO11 - EMAC */
+ 2, /* MIXED1IO12 - EMAC */
+ 2, /* MIXED1IO13 - EMAC */
+ 0, /* MIXED1IO14 - Unused */
+ 3, /* MIXED1IO15 - QSPI */
+ 3, /* MIXED1IO16 - QSPI */
+ 3, /* MIXED1IO17 - QSPI */
+ 3, /* MIXED1IO18 - QSPI */
+ 3, /* MIXED1IO19 - QSPI */
+ 3, /* MIXED1IO20 - QSPI */
+ 0, /* MIXED1IO21 - GPIO */
+ 0, /* MIXED2IO0 - N/A */
+ 0, /* MIXED2IO1 - N/A */
+ 0, /* MIXED2IO2 - N/A */
+ 0, /* MIXED2IO3 - N/A */
+ 0, /* MIXED2IO4 - N/A */
+ 0, /* MIXED2IO5 - N/A */
+ 0, /* MIXED2IO6 - N/A */
+ 0, /* MIXED2IO7 - N/A */
+ 0, /* GPLINMUX48 */
+ 0, /* GPLINMUX49 */
+ 0, /* GPLINMUX50 */
+ 0, /* GPLINMUX51 */
+ 0, /* GPLINMUX52 */
+ 0, /* GPLINMUX53 */
+ 0, /* GPLINMUX54 */
+ 0, /* GPLINMUX55 */
+ 0, /* GPLINMUX56 */
+ 0, /* GPLINMUX57 */
+ 0, /* GPLINMUX58 */
+ 0, /* GPLINMUX59 */
+ 0, /* GPLINMUX60 */
+ 0, /* GPLINMUX61 */
+ 0, /* GPLINMUX62 */
+ 0, /* GPLINMUX63 */
+ 0, /* GPLINMUX64 */
+ 0, /* GPLINMUX65 */
+ 0, /* GPLINMUX66 */
+ 0, /* GPLINMUX67 */
+ 0, /* GPLINMUX68 */
+ 0, /* GPLINMUX69 */
+ 0, /* GPLINMUX70 */
+ 1, /* GPLMUX0 */
+ 1, /* GPLMUX1 */
+ 1, /* GPLMUX2 */
+ 1, /* GPLMUX3 */
+ 1, /* GPLMUX4 */
+ 1, /* GPLMUX5 */
+ 1, /* GPLMUX6 */
+ 1, /* GPLMUX7 */
+ 1, /* GPLMUX8 */
+ 1, /* GPLMUX9 */
+ 1, /* GPLMUX10 */
+ 1, /* GPLMUX11 */
+ 1, /* GPLMUX12 */
+ 1, /* GPLMUX13 */
+ 1, /* GPLMUX14 */
+ 1, /* GPLMUX15 */
+ 1, /* GPLMUX16 */
+ 1, /* GPLMUX17 */
+ 1, /* GPLMUX18 */
+ 1, /* GPLMUX19 */
+ 1, /* GPLMUX20 */
+ 1, /* GPLMUX21 */
+ 1, /* GPLMUX22 */
+ 1, /* GPLMUX23 */
+ 1, /* GPLMUX24 */
+ 1, /* GPLMUX25 */
+ 1, /* GPLMUX26 */
+ 1, /* GPLMUX27 */
+ 1, /* GPLMUX28 */
+ 1, /* GPLMUX29 */
+ 1, /* GPLMUX30 */
+ 1, /* GPLMUX31 */
+ 1, /* GPLMUX32 */
+ 1, /* GPLMUX33 */
+ 1, /* GPLMUX34 */
+ 1, /* GPLMUX35 */
+ 1, /* GPLMUX36 */
+ 1, /* GPLMUX37 */
+ 1, /* GPLMUX38 */
+ 1, /* GPLMUX39 */
+ 1, /* GPLMUX40 */
+ 1, /* GPLMUX41 */
+ 1, /* GPLMUX42 */
+ 1, /* GPLMUX43 */
+ 1, /* GPLMUX44 */
+ 1, /* GPLMUX45 */
+ 1, /* GPLMUX46 */
+ 1, /* GPLMUX47 */
+ 1, /* GPLMUX48 */
+ 1, /* GPLMUX49 */
+ 1, /* GPLMUX50 */
+ 1, /* GPLMUX51 */
+ 1, /* GPLMUX52 */
+ 1, /* GPLMUX53 */
+ 1, /* GPLMUX54 */
+ 1, /* GPLMUX55 */
+ 1, /* GPLMUX56 */
+ 1, /* GPLMUX57 */
+ 1, /* GPLMUX58 */
+ 1, /* GPLMUX59 */
+ 1, /* GPLMUX60 */
+ 1, /* GPLMUX61 */
+ 1, /* GPLMUX62 */
+ 1, /* GPLMUX63 */
+ 1, /* GPLMUX64 */
+ 1, /* GPLMUX65 */
+ 1, /* GPLMUX66 */
+ 1, /* GPLMUX67 */
+ 1, /* GPLMUX68 */
+ 1, /* GPLMUX69 */
+ 1, /* GPLMUX70 */
+ 0, /* NANDUSEFPGA */
+ 0, /* UART0USEFPGA */
+ 0, /* RGMII1USEFPGA */
+ 0, /* SPIS0USEFPGA */
+ 0, /* CAN0USEFPGA */
+ 0, /* I2C0USEFPGA */
+ 0, /* SDMMCUSEFPGA */
+ 0, /* QSPIUSEFPGA */
+ 0, /* SPIS1USEFPGA */
+ 0, /* RGMII0USEFPGA */
+ 0, /* UART1USEFPGA */
+ 0, /* CAN1USEFPGA */
+ 0, /* USB1USEFPGA */
+ 0, /* I2C3USEFPGA */
+ 0, /* I2C2USEFPGA */
+ 0, /* I2C1USEFPGA */
+ 0, /* SPIM1USEFPGA */
+ 0, /* USB0USEFPGA */
+ 0 /* SPIM0USEFPGA */
+};
diff --git a/board/altera/socfpga_cyclone5/pinmux_config.h
b/board/altera/socfpga_cyclone5/pinmux_config.h
new file mode 100644
index 0000000..f278f2b
--- /dev/null
+++ b/board/altera/socfpga_cyclone5/pinmux_config.h
@@ -0,0 +1,54 @@
+/* This file is generated by Preloader Generator */
+
+#ifndef _PRELOADER_PINMUX_CONFIG_H_
+#define _PRELOADER_PINMUX_CONFIG_H_
+
+/*
+ * State of enabling for which IP connected out through the muxing.
+ * Value 1 mean the IP connection is muxed out
+ */
+#define CONFIG_HPS_EMAC0 (0)
+#define CONFIG_HPS_EMAC1 (1)
+#define CONFIG_HPS_USB0 (0)
+#define CONFIG_HPS_USB1 (1)
+#define CONFIG_HPS_NAND (0)
+#define CONFIG_HPS_SDMMC (1)
+#define CONFIG_HPS_QSPI (1)
+#define CONFIG_HPS_UART0 (1)
+#define CONFIG_HPS_UART1 (0)
+#define CONFIG_HPS_TRACE (1)
+#define CONFIG_HPS_I2C0 (1)
+#define CONFIG_HPS_I2C1 (0)
+#define CONFIG_HPS_I2C2 (0)
+#define CONFIG_HPS_I2C3 (0)
+#define CONFIG_HPS_SPIM0 (1)
+#define CONFIG_HPS_SPIM1 (0)
+#define CONFIG_HPS_SPIS0 (0)
+#define CONFIG_HPS_SPIS1 (0)
+#define CONFIG_HPS_CAN0 (1)
+#define CONFIG_HPS_CAN1 (0)
+
+/* IP attribute value (which affected by pin muxing configuration) */
+#define CONFIG_HPS_SDMMC_BUSWIDTH (4)
+
+/* 1 if the pins are connected out */
+#define CONFIG_HPS_QSPI_CS0 (1)
+#define CONFIG_HPS_QSPI_CS1 (0)
+#define CONFIG_HPS_QSPI_CS2 (0)
+#define CONFIG_HPS_QSPI_CS3 (0)
+
+/* UART */
+/* 1 means the pin is mux out or available */
+#define CONFIG_HPS_UART0_TX (1)
+#define CONFIG_HPS_UART0_RX (1)
+#define CONFIG_HPS_UART0_CTS (0)
+#define CONFIG_HPS_UART0_RTS (0)
+#define CONFIG_HPS_UART1_TX (0)
+#define CONFIG_HPS_UART1_RX (0)
+#define CONFIG_HPS_UART1_CTS (0)
+#define CONFIG_HPS_UART1_RTS (0)
+
+/* Pin mux data */
+#define CONFIG_HPS_PINMUX_NUM (207)
+
+#endif /* _PRELOADER_PINMUX_CONFIG_H_ */
diff --git a/include/configs/socfpga_cyclone5.h
b/include/configs/socfpga_cyclone5.h
index be3799b..dd6db9e 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -18,6 +18,7 @@
#define __CONFIG_H
#include <asm/arch/socfpga_base_addrs.h>
+#include "../../board/altera/socfpga_cyclone5/pinmux_config.h"
/*
* High level configuration
--
1.7.9.5
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH v2 1/1] socfpga: Adding System Manager driver which will configure the pin mux for real hardware Cyclone V
2013-06-28 21:20 ` [U-Boot] [PATCH v2 " Chin Liang See
@ 2013-06-28 22:52 ` Wolfgang Denk
2013-07-01 10:42 ` Pavel Machek
1 sibling, 0 replies; 12+ messages in thread
From: Wolfgang Denk @ 2013-06-28 22:52 UTC (permalink / raw)
To: u-boot
Dear Chin Liang See,
In message <1372454448.11240.7.camel@drezykow-VirtualBox.altera.com> you wrote:
> socfpga: Adding System Manager driver which will
> configure the pin mux for real hardware Cyclone V=20
> development kit (not Virtual Platform)
Please fix all your patches: provide a short (max. 50 chars) Subject,
and a useful commit message (_different_ drom the Subject).
Thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Crash programs fail because they are based on the theory that, with
nine women pregnant, you can get a baby a month. - Wernher von Braun
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 1/1] socfpga: Adding System Manager driver which will configure the pin mux for real hardware Cyclone V
2013-06-28 16:10 ` Chin Liang See
@ 2013-07-01 10:39 ` Pavel Machek
2013-07-01 13:38 ` Chin Liang See
0 siblings, 1 reply; 12+ messages in thread
From: Pavel Machek @ 2013-07-01 10:39 UTC (permalink / raw)
To: u-boot
Hi!
> > > --- /dev/null
> > > +++ b/board/altera/socfpga_cyclone5/pinmux_config.c
> > > @@ -0,0 +1,213 @@
> > > +
> > > +#include "pinmux_config.h"
> > > +
> > > +/* pin mux configuration data */
> > > +unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
> > > + 0, /* EMACIO0 - Unused */
> > > + 2, /* EMACIO1 - USB */
> > > + 2, /* EMACIO2 - USB */
> > > + 2, /* EMACIO3 - USB */
> >
> > Is this table auto-generated somehow?
> >
> > If so, comment about that would be nice.
> >
> > If not, perhaps we could put more than one entry on line, to make it
> > shorter?
>
> Yup, its auto generated by tools.
> I will put comment to note this.
Thanks!
You can add Reviewed-by: Pavel Machek <pavel@denx.de> on the next
version.
In future, would it make sense to separate auto-generated and manual
parts? It might be good to have something like pinmux_config.i file
with just inner part of the table...
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH v2 1/1] socfpga: Adding System Manager driver which will configure the pin mux for real hardware Cyclone V
2013-06-28 21:20 ` [U-Boot] [PATCH v2 " Chin Liang See
2013-06-28 22:52 ` Wolfgang Denk
@ 2013-07-01 10:42 ` Pavel Machek
2013-07-01 13:41 ` Chin Liang See
2013-07-01 14:29 ` [U-Boot] [PATCH v3 1/2] socfpga: Adding System Manager driver Chin Liang See
1 sibling, 2 replies; 12+ messages in thread
From: Pavel Machek @ 2013-07-01 10:42 UTC (permalink / raw)
To: u-boot
On Fri 2013-06-28 16:20:48, Chin Liang See wrote:
> socfpga: Adding System Manager driver which will
> configure the pin mux for real hardware Cyclone V
> development kit (not Virtual Platform)
>
> Signed-off-by: Chin Liang See <clsee@altera.com>
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/*
> + * Configure all the pin mux
> + */
As noted before, I'm not sure this is correct english. Otherwise,
patch looks good to me.
Reviewed-by: Pavel Machek <pavel@denx.de>
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 1/1] socfpga: Adding System Manager driver which will configure the pin mux for real hardware Cyclone V
2013-07-01 10:39 ` Pavel Machek
@ 2013-07-01 13:38 ` Chin Liang See
0 siblings, 0 replies; 12+ messages in thread
From: Chin Liang See @ 2013-07-01 13:38 UTC (permalink / raw)
To: u-boot
Hi Pavel,
On Mon, 2013-07-01 at 12:39 +0200, ZY - pavel wrote:
> Hi!
>
> > > > --- /dev/null
> > > > +++ b/board/altera/socfpga_cyclone5/pinmux_config.c
> > > > @@ -0,0 +1,213 @@
> > > > +
> > > > +#include "pinmux_config.h"
> > > > +
> > > > +/* pin mux configuration data */
> > > > +unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
> > > > + 0, /* EMACIO0 - Unused */
> > > > + 2, /* EMACIO1 - USB */
> > > > + 2, /* EMACIO2 - USB */
> > > > + 2, /* EMACIO3 - USB */
> > >
> > > Is this table auto-generated somehow?
> > >
> > > If so, comment about that would be nice.
> > >
> > > If not, perhaps we could put more than one entry on line, to make it
> > > shorter?
> >
> > Yup, its auto generated by tools.
> > I will put comment to note this.
>
> Thanks!
>
> You can add Reviewed-by: Pavel Machek <pavel@denx.de> on the next
> version.
>
Thanks
> In future, would it make sense to separate auto-generated and manual
> parts? It might be good to have something like pinmux_config.i file
> with just inner part of the table...
>
Sure, I will split them into 2 patches on next version
Chin Liang
> Pavel
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH v2 1/1] socfpga: Adding System Manager driver which will configure the pin mux for real hardware Cyclone V
2013-07-01 10:42 ` Pavel Machek
@ 2013-07-01 13:41 ` Chin Liang See
2013-07-02 11:37 ` Pavel Machek
2013-07-01 14:29 ` [U-Boot] [PATCH v3 1/2] socfpga: Adding System Manager driver Chin Liang See
1 sibling, 1 reply; 12+ messages in thread
From: Chin Liang See @ 2013-07-01 13:41 UTC (permalink / raw)
To: u-boot
Hi Pavel,
On Mon, 2013-07-01 at 12:42 +0200, ZY - pavel wrote:
> On Fri 2013-06-28 16:20:48, Chin Liang See wrote:
> > socfpga: Adding System Manager driver which will
> > configure the pin mux for real hardware Cyclone V
> > development kit (not Virtual Platform)
> >
> > Signed-off-by: Chin Liang See <clsee@altera.com>
>
>
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +/*
> > + * Configure all the pin mux
> > + */
>
> As noted before, I'm not sure this is correct english. Otherwise,
> patch looks good to me.
>
Sorry as I thought I already done that.
Let me fix it on next revision.
Chin Liang
> Reviewed-by: Pavel Machek <pavel@denx.de>
> Pavel
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH v3 1/2] socfpga: Adding System Manager driver
2013-07-01 10:42 ` Pavel Machek
2013-07-01 13:41 ` Chin Liang See
@ 2013-07-01 14:29 ` Chin Liang See
2013-07-01 14:31 ` [U-Boot] [PATCH v3 2/2] " Chin Liang See
1 sibling, 1 reply; 12+ messages in thread
From: Chin Liang See @ 2013-07-01 14:29 UTC (permalink / raw)
To: u-boot
socfpga: Adding System Manager driver which
will configure the pin mux for real hardware Cyclone V
development kit (not Virtual Platform)
Signed-off-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
---
arch/arm/cpu/armv7/socfpga/Makefile | 2 +-
arch/arm/cpu/armv7/socfpga/spl.c | 6 +++
arch/arm/cpu/armv7/socfpga/system_manager.c | 41
++++++++++++++++++++
.../include/asm/arch-socfpga/socfpga_base_addrs.h | 1 +
arch/arm/include/asm/arch-socfpga/system_manager.h | 34
++++++++++++++++
board/altera/socfpga_cyclone5/Makefile | 4 +-
include/configs/socfpga_cyclone5.h | 1 +
7 files changed, 87 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/system_manager.c
create mode 100644 arch/arm/include/asm/arch-socfpga/system_manager.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index 518e67a..cf2829a 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
-COBJS-y := misc.o timer.o reset_manager.o
+COBJS-y := misc.o timer.o reset_manager.o system_manager.o
COBJS-$(CONFIG_SPL_BUILD) += spl.o
COBJS := $(COBJS-y)
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c
b/arch/arm/cpu/armv7/socfpga/spl.c
index 84216eb..28d8c99 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -23,6 +23,7 @@
#include <image.h>
#include <asm/arch/reset_manager.h>
#include <spl.h>
+#include <asm/arch/system_manager.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -36,6 +37,11 @@ u32 spl_boot_device(void)
*/
void spl_board_init(void)
{
+#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
+ /* configure the pin muxing through system manager */
+ sysmgr_pinmux_init();
+#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
+
/* de-assert reset for peripherals and bridges based on handoff */
reset_deassert_peripherals_handoff();
diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c
b/arch/arm/cpu/armv7/socfpga/system_manager.c
new file mode 100644
index 0000000..d893e97
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/system_manager.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright Altera Corporation (C) 2013. All rights reserved
+ *
+ * This program is free software; you can redistribute it
+ * and/or modify it under the terms and conditions of the
+ * GNU General Public License, version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program. If not, see
+ * <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/system_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Configure all the pin muxes
+ */
+void sysmgr_pinmux_init(void)
+{
+ unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET;
+
+ const unsigned long *pval = sys_mgr_init_table;
+ unsigned long i;
+
+ for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table);
+ i++, offset += sizeof(unsigned long)) {
+ writel(*pval++, (SOCFPGA_SYSMGR_ADDRESS + offset));
+ }
+}
+
+
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
index f353eb2..819c280 100644
--- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
+++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
@@ -23,5 +23,6 @@
#define SOCFPGA_UART1_ADDRESS 0xffc03000
#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
#endif /* _SOCFPGA_BASE_ADDRS_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h
b/arch/arm/include/asm/arch-socfpga/system_manager.h
new file mode 100644
index 0000000..ef9e464
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/system_manager.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright Altera Corporation (C) 2013. All rights reserved
+ *
+ * This program is free software; you can redistribute it
+ * and/or modify it under the terms and conditions of the
+ * GNU General Public License, version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program. If not, see
+ * <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SYSTEM_MANAGER_H_
+#define _SYSTEM_MANAGER_H_
+
+#ifndef __ASSEMBLY__
+
+void sysmgr_pinmux_init(void);
+
+/* declaration for handoff table type */
+extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM];
+
+#endif
+
+
+#define CONFIG_SYSMGR_PINMUXGRP_OFFSET (0x400)
+
+#endif /* _SYSTEM_MANAGER_H_ */
diff --git a/board/altera/socfpga_cyclone5/Makefile
b/board/altera/socfpga_cyclone5/Makefile
index 43bbc37..3092387 100644
--- a/board/altera/socfpga_cyclone5/Makefile
+++ b/board/altera/socfpga_cyclone5/Makefile
@@ -26,8 +26,10 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
-COBJS := socfpga_cyclone5.o
+COBJS-y := socfpga_cyclone5.o
+COBJS-$(CONFIG_SPL_BUILD) += pinmux_config.o
+COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/include/configs/socfpga_cyclone5.h
b/include/configs/socfpga_cyclone5.h
index be3799b..dd6db9e 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -18,6 +18,7 @@
#define __CONFIG_H
#include <asm/arch/socfpga_base_addrs.h>
+#include "../../board/altera/socfpga_cyclone5/pinmux_config.h"
/*
* High level configuration
--
1.7.9.5
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH v3 2/2] socfpga: Adding System Manager driver
2013-07-01 14:29 ` [U-Boot] [PATCH v3 1/2] socfpga: Adding System Manager driver Chin Liang See
@ 2013-07-01 14:31 ` Chin Liang See
0 siblings, 0 replies; 12+ messages in thread
From: Chin Liang See @ 2013-07-01 14:31 UTC (permalink / raw)
To: u-boot
socfpga: Adding the generated pin mux
configuration by Preloader Generator tool
Signed-off-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
---
board/altera/socfpga_cyclone5/pinmux_config.c | 214
+++++++++++++++++++++++++
board/altera/socfpga_cyclone5/pinmux_config.h | 54 +++++++
2 files changed, 268 insertions(+)
create mode 100644 board/altera/socfpga_cyclone5/pinmux_config.c
create mode 100644 board/altera/socfpga_cyclone5/pinmux_config.h
diff --git a/board/altera/socfpga_cyclone5/pinmux_config.c
b/board/altera/socfpga_cyclone5/pinmux_config.c
new file mode 100644
index 0000000..8b09005
--- /dev/null
+++ b/board/altera/socfpga_cyclone5/pinmux_config.c
@@ -0,0 +1,214 @@
+/* This file is generated by Preloader Generator */
+
+#include "pinmux_config.h"
+
+/* pin mux configuration data */
+unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
+ 0, /* EMACIO0 - Unused */
+ 2, /* EMACIO1 - USB */
+ 2, /* EMACIO2 - USB */
+ 2, /* EMACIO3 - USB */
+ 2, /* EMACIO4 - USB */
+ 2, /* EMACIO5 - USB */
+ 2, /* EMACIO6 - USB */
+ 2, /* EMACIO7 - USB */
+ 2, /* EMACIO8 - USB */
+ 0, /* EMACIO9 - Unused */
+ 2, /* EMACIO10 - USB */
+ 2, /* EMACIO11 - USB */
+ 2, /* EMACIO12 - USB */
+ 2, /* EMACIO13 - USB */
+ 0, /* EMACIO14 - N/A */
+ 0, /* EMACIO15 - N/A */
+ 0, /* EMACIO16 - N/A */
+ 0, /* EMACIO17 - N/A */
+ 0, /* EMACIO18 - N/A */
+ 0, /* EMACIO19 - N/A */
+ 3, /* FLASHIO0 - SDMMC */
+ 3, /* FLASHIO1 - SDMMC */
+ 3, /* FLASHIO2 - SDMMC */
+ 3, /* FLASHIO3 - SDMMC */
+ 0, /* FLASHIO4 - SDMMC */
+ 0, /* FLASHIO5 - SDMMC */
+ 0, /* FLASHIO6 - SDMMC */
+ 0, /* FLASHIO7 - SDMMC */
+ 0, /* FLASHIO8 - SDMMC */
+ 3, /* FLASHIO9 - SDMMC */
+ 3, /* FLASHIO10 - SDMMC */
+ 3, /* FLASHIO11 - SDMMC */
+ 3, /* GENERALIO0 - TRACE */
+ 3, /* GENERALIO1 - TRACE */
+ 3, /* GENERALIO2 - TRACE */
+ 3, /* GENERALIO3 - TRACE */
+ 3, /* GENERALIO4 - TRACE */
+ 3, /* GENERALIO5 - TRACE */
+ 3, /* GENERALIO6 - TRACE */
+ 3, /* GENERALIO7 - TRACE */
+ 3, /* GENERALIO8 - TRACE */
+ 3, /* GENERALIO9 - SPIM0 */
+ 3, /* GENERALIO10 - SPIM0 */
+ 3, /* GENERALIO11 - SPIM0 */
+ 3, /* GENERALIO12 - SPIM0 */
+ 2, /* GENERALIO13 - CAN0 */
+ 2, /* GENERALIO14 - CAN0 */
+ 3, /* GENERALIO15 - I2C0 */
+ 3, /* GENERALIO16 - I2C0 */
+ 2, /* GENERALIO17 - UART0 */
+ 2, /* GENERALIO18 - UART0 */
+ 0, /* GENERALIO19 - N/A */
+ 0, /* GENERALIO20 - N/A */
+ 0, /* GENERALIO21 - N/A */
+ 0, /* GENERALIO22 - N/A */
+ 0, /* GENERALIO23 - N/A */
+ 0, /* GENERALIO24 - N/A */
+ 0, /* GENERALIO25 - N/A */
+ 0, /* GENERALIO26 - N/A */
+ 0, /* GENERALIO27 - N/A */
+ 0, /* GENERALIO28 - N/A */
+ 0, /* GENERALIO29 - N/A */
+ 0, /* GENERALIO30 - N/A */
+ 0, /* GENERALIO31 - N/A */
+ 2, /* MIXED1IO0 - EMAC */
+ 2, /* MIXED1IO1 - EMAC */
+ 2, /* MIXED1IO2 - EMAC */
+ 2, /* MIXED1IO3 - EMAC */
+ 2, /* MIXED1IO4 - EMAC */
+ 2, /* MIXED1IO5 - EMAC */
+ 2, /* MIXED1IO6 - EMAC */
+ 2, /* MIXED1IO7 - EMAC */
+ 2, /* MIXED1IO8 - EMAC */
+ 2, /* MIXED1IO9 - EMAC */
+ 2, /* MIXED1IO10 - EMAC */
+ 2, /* MIXED1IO11 - EMAC */
+ 2, /* MIXED1IO12 - EMAC */
+ 2, /* MIXED1IO13 - EMAC */
+ 0, /* MIXED1IO14 - Unused */
+ 3, /* MIXED1IO15 - QSPI */
+ 3, /* MIXED1IO16 - QSPI */
+ 3, /* MIXED1IO17 - QSPI */
+ 3, /* MIXED1IO18 - QSPI */
+ 3, /* MIXED1IO19 - QSPI */
+ 3, /* MIXED1IO20 - QSPI */
+ 0, /* MIXED1IO21 - GPIO */
+ 0, /* MIXED2IO0 - N/A */
+ 0, /* MIXED2IO1 - N/A */
+ 0, /* MIXED2IO2 - N/A */
+ 0, /* MIXED2IO3 - N/A */
+ 0, /* MIXED2IO4 - N/A */
+ 0, /* MIXED2IO5 - N/A */
+ 0, /* MIXED2IO6 - N/A */
+ 0, /* MIXED2IO7 - N/A */
+ 0, /* GPLINMUX48 */
+ 0, /* GPLINMUX49 */
+ 0, /* GPLINMUX50 */
+ 0, /* GPLINMUX51 */
+ 0, /* GPLINMUX52 */
+ 0, /* GPLINMUX53 */
+ 0, /* GPLINMUX54 */
+ 0, /* GPLINMUX55 */
+ 0, /* GPLINMUX56 */
+ 0, /* GPLINMUX57 */
+ 0, /* GPLINMUX58 */
+ 0, /* GPLINMUX59 */
+ 0, /* GPLINMUX60 */
+ 0, /* GPLINMUX61 */
+ 0, /* GPLINMUX62 */
+ 0, /* GPLINMUX63 */
+ 0, /* GPLINMUX64 */
+ 0, /* GPLINMUX65 */
+ 0, /* GPLINMUX66 */
+ 0, /* GPLINMUX67 */
+ 0, /* GPLINMUX68 */
+ 0, /* GPLINMUX69 */
+ 0, /* GPLINMUX70 */
+ 1, /* GPLMUX0 */
+ 1, /* GPLMUX1 */
+ 1, /* GPLMUX2 */
+ 1, /* GPLMUX3 */
+ 1, /* GPLMUX4 */
+ 1, /* GPLMUX5 */
+ 1, /* GPLMUX6 */
+ 1, /* GPLMUX7 */
+ 1, /* GPLMUX8 */
+ 1, /* GPLMUX9 */
+ 1, /* GPLMUX10 */
+ 1, /* GPLMUX11 */
+ 1, /* GPLMUX12 */
+ 1, /* GPLMUX13 */
+ 1, /* GPLMUX14 */
+ 1, /* GPLMUX15 */
+ 1, /* GPLMUX16 */
+ 1, /* GPLMUX17 */
+ 1, /* GPLMUX18 */
+ 1, /* GPLMUX19 */
+ 1, /* GPLMUX20 */
+ 1, /* GPLMUX21 */
+ 1, /* GPLMUX22 */
+ 1, /* GPLMUX23 */
+ 1, /* GPLMUX24 */
+ 1, /* GPLMUX25 */
+ 1, /* GPLMUX26 */
+ 1, /* GPLMUX27 */
+ 1, /* GPLMUX28 */
+ 1, /* GPLMUX29 */
+ 1, /* GPLMUX30 */
+ 1, /* GPLMUX31 */
+ 1, /* GPLMUX32 */
+ 1, /* GPLMUX33 */
+ 1, /* GPLMUX34 */
+ 1, /* GPLMUX35 */
+ 1, /* GPLMUX36 */
+ 1, /* GPLMUX37 */
+ 1, /* GPLMUX38 */
+ 1, /* GPLMUX39 */
+ 1, /* GPLMUX40 */
+ 1, /* GPLMUX41 */
+ 1, /* GPLMUX42 */
+ 1, /* GPLMUX43 */
+ 1, /* GPLMUX44 */
+ 1, /* GPLMUX45 */
+ 1, /* GPLMUX46 */
+ 1, /* GPLMUX47 */
+ 1, /* GPLMUX48 */
+ 1, /* GPLMUX49 */
+ 1, /* GPLMUX50 */
+ 1, /* GPLMUX51 */
+ 1, /* GPLMUX52 */
+ 1, /* GPLMUX53 */
+ 1, /* GPLMUX54 */
+ 1, /* GPLMUX55 */
+ 1, /* GPLMUX56 */
+ 1, /* GPLMUX57 */
+ 1, /* GPLMUX58 */
+ 1, /* GPLMUX59 */
+ 1, /* GPLMUX60 */
+ 1, /* GPLMUX61 */
+ 1, /* GPLMUX62 */
+ 1, /* GPLMUX63 */
+ 1, /* GPLMUX64 */
+ 1, /* GPLMUX65 */
+ 1, /* GPLMUX66 */
+ 1, /* GPLMUX67 */
+ 1, /* GPLMUX68 */
+ 1, /* GPLMUX69 */
+ 1, /* GPLMUX70 */
+ 0, /* NANDUSEFPGA */
+ 0, /* UART0USEFPGA */
+ 0, /* RGMII1USEFPGA */
+ 0, /* SPIS0USEFPGA */
+ 0, /* CAN0USEFPGA */
+ 0, /* I2C0USEFPGA */
+ 0, /* SDMMCUSEFPGA */
+ 0, /* QSPIUSEFPGA */
+ 0, /* SPIS1USEFPGA */
+ 0, /* RGMII0USEFPGA */
+ 0, /* UART1USEFPGA */
+ 0, /* CAN1USEFPGA */
+ 0, /* USB1USEFPGA */
+ 0, /* I2C3USEFPGA */
+ 0, /* I2C2USEFPGA */
+ 0, /* I2C1USEFPGA */
+ 0, /* SPIM1USEFPGA */
+ 0, /* USB0USEFPGA */
+ 0 /* SPIM0USEFPGA */
+};
diff --git a/board/altera/socfpga_cyclone5/pinmux_config.h
b/board/altera/socfpga_cyclone5/pinmux_config.h
new file mode 100644
index 0000000..f278f2b
--- /dev/null
+++ b/board/altera/socfpga_cyclone5/pinmux_config.h
@@ -0,0 +1,54 @@
+/* This file is generated by Preloader Generator */
+
+#ifndef _PRELOADER_PINMUX_CONFIG_H_
+#define _PRELOADER_PINMUX_CONFIG_H_
+
+/*
+ * State of enabling for which IP connected out through the muxing.
+ * Value 1 mean the IP connection is muxed out
+ */
+#define CONFIG_HPS_EMAC0 (0)
+#define CONFIG_HPS_EMAC1 (1)
+#define CONFIG_HPS_USB0 (0)
+#define CONFIG_HPS_USB1 (1)
+#define CONFIG_HPS_NAND (0)
+#define CONFIG_HPS_SDMMC (1)
+#define CONFIG_HPS_QSPI (1)
+#define CONFIG_HPS_UART0 (1)
+#define CONFIG_HPS_UART1 (0)
+#define CONFIG_HPS_TRACE (1)
+#define CONFIG_HPS_I2C0 (1)
+#define CONFIG_HPS_I2C1 (0)
+#define CONFIG_HPS_I2C2 (0)
+#define CONFIG_HPS_I2C3 (0)
+#define CONFIG_HPS_SPIM0 (1)
+#define CONFIG_HPS_SPIM1 (0)
+#define CONFIG_HPS_SPIS0 (0)
+#define CONFIG_HPS_SPIS1 (0)
+#define CONFIG_HPS_CAN0 (1)
+#define CONFIG_HPS_CAN1 (0)
+
+/* IP attribute value (which affected by pin muxing configuration) */
+#define CONFIG_HPS_SDMMC_BUSWIDTH (4)
+
+/* 1 if the pins are connected out */
+#define CONFIG_HPS_QSPI_CS0 (1)
+#define CONFIG_HPS_QSPI_CS1 (0)
+#define CONFIG_HPS_QSPI_CS2 (0)
+#define CONFIG_HPS_QSPI_CS3 (0)
+
+/* UART */
+/* 1 means the pin is mux out or available */
+#define CONFIG_HPS_UART0_TX (1)
+#define CONFIG_HPS_UART0_RX (1)
+#define CONFIG_HPS_UART0_CTS (0)
+#define CONFIG_HPS_UART0_RTS (0)
+#define CONFIG_HPS_UART1_TX (0)
+#define CONFIG_HPS_UART1_RX (0)
+#define CONFIG_HPS_UART1_CTS (0)
+#define CONFIG_HPS_UART1_RTS (0)
+
+/* Pin mux data */
+#define CONFIG_HPS_PINMUX_NUM (207)
+
+#endif /* _PRELOADER_PINMUX_CONFIG_H_ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH v2 1/1] socfpga: Adding System Manager driver which will configure the pin mux for real hardware Cyclone V
2013-07-01 13:41 ` Chin Liang See
@ 2013-07-02 11:37 ` Pavel Machek
0 siblings, 0 replies; 12+ messages in thread
From: Pavel Machek @ 2013-07-02 11:37 UTC (permalink / raw)
To: u-boot
On Mon 2013-07-01 08:41:15, Chin Liang See wrote:
> Hi Pavel,
>
> On Mon, 2013-07-01 at 12:42 +0200, ZY - pavel wrote:
> > On Fri 2013-06-28 16:20:48, Chin Liang See wrote:
> > > socfpga: Adding System Manager driver which will
> > > configure the pin mux for real hardware Cyclone V
> > > development kit (not Virtual Platform)
> > >
> > > Signed-off-by: Chin Liang See <clsee@altera.com>
> >
> >
> > > +DECLARE_GLOBAL_DATA_PTR;
> > > +
> > > +/*
> > > + * Configure all the pin mux
> > > + */
> >
> > As noted before, I'm not sure this is correct english. Otherwise,
> > patch looks good to me.
> >
>
> Sorry as I thought I already done that.
> Let me fix it on next revision.
Thanks!
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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2013-06-27 13:35 ` [U-Boot] [PATCH 1/1] socfpga: Adding System Manager driver which will configure the pin mux for real hardware Cyclone V Chin Liang See
2013-06-28 11:40 ` Pavel Machek
2013-06-28 16:10 ` Chin Liang See
2013-07-01 10:39 ` Pavel Machek
2013-07-01 13:38 ` Chin Liang See
2013-06-28 21:20 ` [U-Boot] [PATCH v2 " Chin Liang See
2013-06-28 22:52 ` Wolfgang Denk
2013-07-01 10:42 ` Pavel Machek
2013-07-01 13:41 ` Chin Liang See
2013-07-02 11:37 ` Pavel Machek
2013-07-01 14:29 ` [U-Boot] [PATCH v3 1/2] socfpga: Adding System Manager driver Chin Liang See
2013-07-01 14:31 ` [U-Boot] [PATCH v3 2/2] " Chin Liang See
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