From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kuo-Jung Su Date: Thu, 4 Jul 2013 11:40:33 +0800 Subject: [U-Boot] [PATCH v6 01/12] arm: dma_alloc_coherent: malloc() -> memalign() In-Reply-To: <1372909244-25211-1-git-send-email-dantesu@gmail.com> References: <1372909244-25211-1-git-send-email-dantesu@gmail.com> Message-ID: <1372909244-25211-2-git-send-email-dantesu@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Kuo-Jung Su Even though the MMU/D-cache is off, some DMA engines still expect strict address alignment. For example, the incoming Faraday FTMAC110 & FTGMAC100 ethernet controllers expect the tx/rx descriptors should always be aligned to 16-bytes boundary. Signed-off-by: Kuo-Jung Su CC: Albert ARIBAUD --- Changes for v6: - Nothing updates Changes for v5: - Initial commit, which is separated from "arm: add MMU/D-Cache support for Faraday cores" arch/arm/include/asm/dma-mapping.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 5bbb0a0..a11178f 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -32,7 +32,7 @@ enum dma_data_direction { static void *dma_alloc_coherent(size_t len, unsigned long *handle) { - *handle = (unsigned long)malloc(len); + *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len); return (void *)*handle; } -- 1.7.9.5