[U-Boot] [PATCH V2 2/2] i.MX6: nitrogen6x: Don't bother setting PLL3(480) PFD1 divisor

[Eric Nelson <eric.nelson@boundarydevices.com>]

This clock isn't feeding anything under U-Boot, so there's no
point in changing it from power-on default.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
 Patch V1 changed the settings to use new macros
 V2 simply discards the code

 board/boundary/nitrogen6x/nitrogen6x.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index 79ab449..3c24367 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -622,7 +622,6 @@ int board_video_skip(void)
 static void setup_display(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 	int reg;
 
@@ -633,10 +632,6 @@ static void setup_display(void)
 	reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
 	writel(reg, &mxc_ccm->CCGR3);
 
-	/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
-	writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
-	writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
-
 	/* set LDB0, LDB1 clk select to 011/011 */
 	reg = readl(&mxc_ccm->cs2cdr);
 	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
-- 
1.8.1.2