From: Thierry Reding <thierry.reding@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 2/2] Tegra114: Do not program CPCON field for PLLX
Date: Mon, 23 Sep 2013 22:07:50 +0200 [thread overview]
Message-ID: <1379966870-4087-2-git-send-email-treding@nvidia.com> (raw)
In-Reply-To: <1379966870-4087-1-git-send-email-treding@nvidia.com>
PLLX no longer has the CPCON field on Tegra114, so do not attempt to
program it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- new patch
arch/arm/cpu/arm720t/tegra-common/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
index aa1e04f..5ab2ebf 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -135,6 +135,7 @@ void adjust_pllp_out_freqs(void)
int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
u32 divp, u32 cpcon)
{
+ int chip = tegra_get_chip();
u32 reg;
/* If PLLX is already enabled, just return */
@@ -151,7 +152,8 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
writel(reg, &pll->pll_base);
/* Set cpcon to PLLX_MISC */
- reg = (cpcon << PLL_CPCON_SHIFT);
+ if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
+ reg = (cpcon << PLL_CPCON_SHIFT);
/* Set dccon to PLLX_MISC if freq > 600MHz */
if (divn > 600)
--
1.8.4
next prev parent reply other threads:[~2013-09-23 20:07 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-23 20:07 [U-Boot] [PATCH v2 1/2] Tegra114: Fix PLLX M, N, P init settings Thierry Reding
2013-09-23 20:07 ` Thierry Reding [this message]
2013-09-30 21:25 ` [U-Boot] [PATCH v2 2/2] Tegra114: Do not program CPCON field for PLLX Tom Warren
2013-10-01 15:06 ` Thierry Reding
2013-10-01 18:02 ` Tom Warren
2013-09-23 21:45 ` [U-Boot] [PATCH v2 1/2] Tegra114: Fix PLLX M, N, P init settings Stephen Warren
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