From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thierry Reding Date: Mon, 23 Sep 2013 22:07:50 +0200 Subject: [U-Boot] [PATCH v2 2/2] Tegra114: Do not program CPCON field for PLLX In-Reply-To: <1379966870-4087-1-git-send-email-treding@nvidia.com> References: <1379966870-4087-1-git-send-email-treding@nvidia.com> Message-ID: <1379966870-4087-2-git-send-email-treding@nvidia.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de PLLX no longer has the CPCON field on Tegra114, so do not attempt to program it. Signed-off-by: Thierry Reding --- Changes in v2: - new patch arch/arm/cpu/arm720t/tegra-common/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index aa1e04f..5ab2ebf 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -135,6 +135,7 @@ void adjust_pllp_out_freqs(void) int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, u32 divp, u32 cpcon) { + int chip = tegra_get_chip(); u32 reg; /* If PLLX is already enabled, just return */ @@ -151,7 +152,8 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, writel(reg, &pll->pll_base); /* Set cpcon to PLLX_MISC */ - reg = (cpcon << PLL_CPCON_SHIFT); + if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30) + reg = (cpcon << PLL_CPCON_SHIFT); /* Set dccon to PLLX_MISC if freq > 600MHz */ if (divn > 600) -- 1.8.4