[U-Boot] [PATCH v8] nand: add Faraday FTNANDC021 NAND controller support

[Kuo-Jung Su <dantesu@gmail.com>]

From: Kuo-Jung Su <dantesu@faraday-tech.com>

Faraday FTNANDC021 is an integrated NAND flash controller.
It use a build-in command table to abstract the underlying
NAND flash control logic.

For example:

Issuing a command 0x10 to FTNANDC021 would result in
a page write + a read status operation.

Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Albert ARIBAUD <albert.u.boot@aribaud.net>
CC: Scott Wood <scottwood@freescale.com>
---
Changes for v8:
   - Add ftnandc021 spl driver
   - Drop '#include <asm/unaligned.h>'
   - Coding style cleanup
   - Update NAND flash ecc layout
   - Split from Faraday A36x patch series

Changes for v7:
   - ftnandc021.[ch]: Update license to use SPDX identifiers.
   - ftnandc021.c: put_unaligned() -> memcpy()
   - ftnandc021.c: update ecc relatived function prototypes to
     fix compile warnnings.

Changes for v6:
   - Update README for CONFIG_SYS_FTNANDC021_TIMING
   - Remove illegal type-punning by introducing
     put_unaligned() & get_unaligned().

Changes for v5 (Part of A360/A369 patch series):
   - Coding Style cleanup:
     struct chip_regs __iomem *regs -> struct chip_regs *regs
   - For there is a strong dependancy between this and A360/A369 patch
     series, it had been chained back to A360/A369 patch series.
   - The latest nand_base requires the ecc.strength to be set properlly,
     so this patch adds ecc.strength setting accroding to ECC algorithm.

Changes for v5 (Standalone):
   - Update README for the description of CONFIG_SYS_FTNANDC021_TIMING.
   - Drop redundant white space. (i.e. if (mtd->writesize >= ' '4096))

Changes for v4:
   - Make it a separate patch, rather then a part of
     Faraday A36x patch series
   - Drop the faraday/nand.h to remove dependency to
     Faraday A36x patch series.
   - CONFIG_SYS_NAND_TIMING -> CONFIG_SYS_FTNANDC021_TIMING
   - Remove non-ECC code.
   - Implement private hwecc read/write_page functions
     to get rid of .eccpos & .eccbytes.
   - Use macro constants for timeout control

Changes for v3:
   - Coding Style cleanup.
   - Drop macros for wirtel()/readl(), call them directly.
   - Always insert a blank line between declarations and code.
   - Replace all the infinite wait loop with a timeout.
   - Add '__iomem' to all the declaration of HW register pointers.
   - Re-write this driver with ECC enabled and correct column address
     handling for OOB read/write.
   - Fix issuses addressed by Scott.

Changes for v2:
   - Coding Style cleanup.
   - Use readl(), writel(), clrsetbits_le32() to replace REG() macros.
   - Use structure based hardware registers to replace the macro constants.
   - Replace BIT() with BIT_MASK().

 README                            |    6 +
 drivers/mtd/nand/Makefile         |    2 +
 drivers/mtd/nand/ftnandc021.c     |  608 +++++++++++++++++++++++++++++++++++++
 drivers/mtd/nand/ftnandc021_spl.c |  203 +++++++++++++
 include/faraday/ftnandc021.h      |  151 +++++++++
 5 files changed, 970 insertions(+)
 create mode 100644 drivers/mtd/nand/ftnandc021.c
 create mode 100644 drivers/mtd/nand/ftnandc021_spl.c
 create mode 100644 include/faraday/ftnandc021.h

diff --git a/README b/README
index 5def773..a8d3039 100644
--- a/README
+++ b/README
@@ -4227,6 +4227,12 @@ Low Level (hardware related) configuration options:
 		- drivers/mtd/nand/ndfc.c
 		- drivers/mtd/nand/mxc_nand.c

+- CONFIG_SYS_FTNANDC021_TIMING
+		This option specifies an array of customized timing parameters
+		for Faraday FTNANDC021 NAND flash controller.
+		e.g.
+		#define CONFIG_SYS_FTNANDC021_TIMING { 0x02240264, 0x42054209 }
+
 - CONFIG_SYS_NDFC_EBC0_CFG
 		Sets the EBC0_CFG register for the NDFC. If not defined
 		a default value will be used.
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index e145cd1..7e6d441 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
 obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
 obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
 obj-$(CONFIG_NAND_FSMC) += fsmc_nand.o
+obj-$(CONFIG_NAND_FTNANDC021) += ftnandc021.o
 obj-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
 obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
 obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
@@ -66,6 +67,7 @@ else  # minimal SPL drivers

 obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o
 obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o
+obj-$(CONFIG_NAND_FTNANDC021) += ftnandc021_spl.o
 obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o

 endif # drivers
diff --git a/drivers/mtd/nand/ftnandc021.c b/drivers/mtd/nand/ftnandc021.c
new file mode 100644
index 0000000..71b1dc3
--- /dev/null
+++ b/drivers/mtd/nand/ftnandc021.c
@@ -0,0 +1,608 @@
+/*
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. <http://www.faraday-tech.com/tw/>
+ * Kuo-Jung Su <dantesu@gmail.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <malloc.h>
+#include <faraday/ftnandc021.h>
+
+#define CFG_CMD_TIMEOUT     200
+
+struct ftnandc021_chip {
+	struct mtd_info *mtd;
+	struct ftnandc021_regs *regs;
+	int col;    /* current column address */
+	int row;    /* current row address/page index */
+	int cmd;    /* current NAND command code */
+};
+
+static struct nand_ecclayout nand_ecclayout = {
+	.oobavail = 3,
+	.oobfree = {
+		{ 9, 3 },
+	},
+};
+
+static struct nand_ecclayout nand_4k_ecclayout = {
+	.oobavail = 7,
+	.oobfree = {
+		{ 9, 7 },
+	},
+};
+
+static int ftnandc021_ckst(struct ftnandc021_chip *priv)
+{
+	struct ftnandc021_regs *regs = priv->regs;
+	uint32_t st = readl(&regs->idr[1]);
+
+	if (st & NAND_STATUS_FAIL)
+		return -EIO;
+
+	if (!(st & NAND_STATUS_READY))
+		return -EBUSY;
+
+	if (!(st & NAND_STATUS_WP))
+		return -EIO;
+
+	return 0;
+}
+
+static int ftnandc021_wait(struct ftnandc021_chip *priv)
+{
+	struct ftnandc021_regs *regs = priv->regs;
+	int err = -1;
+	ulong ts;
+
+	for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
+		if (readl(&regs->sr) & SR_ECC) {
+			err = -2;
+			break;
+		}
+		if (!(readl(&regs->acr) & ACR_START)) {
+			err = 0;
+			break;
+		}
+	}
+
+	switch (err) {
+	case -2:
+		printf("ftnandc021: ecc timeout\n");
+		break;
+	case -1:
+		printf("ftnandc021: cmd timeout\n");
+		break;
+	default:
+		break;
+	}
+
+	return err ? -ETIMEDOUT : 0;
+}
+
+static int ftnandc021_read_page(struct mtd_info *mtd,
+	struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
+{
+	chip->read_buf(mtd, buf, mtd->writesize);
+	return 0;
+}
+
+static int ftnandc021_write_page(struct mtd_info *mtd,
+	struct nand_chip *chip, const uint8_t *buf, int oob_required)
+{
+	chip->write_buf(mtd, buf, mtd->writesize);
+	return 0;
+}
+
+static int ftnandc021_read_page_raw(struct mtd_info *mtd,
+	struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
+{
+	printf("ftnandc021: read_page_raw is not supported\n");
+	return -EIO;
+}
+
+static int ftnandc021_write_page_raw(struct mtd_info *mtd,
+	struct nand_chip *chip, const uint8_t *buf, int oob_required)
+{
+	printf("ftnandc021: write_page_raw is not supported\n");
+	return -EIO;
+}
+
+static int ftnandc021_command(struct ftnandc021_chip *priv, uint32_t cmd)
+{
+	struct ftnandc021_regs *regs = priv->regs;
+	int ret = 0;
+
+	writel(ACR_START | ACR_CMD(cmd), &regs->acr);
+
+	switch (cmd) {
+	case FTNANDC021_CMD_RDPG:
+	case FTNANDC021_CMD_WRPG:
+		break;
+	case FTNANDC021_CMD_ERBLK:
+	case FTNANDC021_CMD_WROOB:
+		ret = ftnandc021_wait(priv) || ftnandc021_ckst(priv);
+		break;
+	default:
+		ret = ftnandc021_wait(priv);
+	}
+
+	return ret;
+}
+
+/*
+ * Check hardware register for wait status. Returns 1 if device is ready,
+ * 0 if it is still busy.
+ */
+static int ftnandc021_dev_ready(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct ftnandc021_chip *priv = chip->priv;
+	struct ftnandc021_regs *regs = priv->regs;
+	int ret = 1;
+
+	if (ftnandc021_wait(priv))
+		ret = 0;
+	else if (!(readl(&regs->sr) & SR_READY))
+		ret = 0;
+
+	return ret;
+}
+
+static int ftnandc021_pio_wait(struct ftnandc021_chip *priv)
+{
+	struct ftnandc021_regs *regs = priv->regs;
+	int ret = -ETIMEDOUT;
+	ulong ts;
+
+	for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
+		if (!(readl(&regs->ior) & IOR_READY))
+			continue;
+		ret = 0;
+		break;
+	}
+
+	if (ret)
+		printf("ftnandc021: pio timeout\n");
+
+	return ret;
+}
+
+static void ftnandc021_get_oob(struct mtd_info *mtd,
+	uint8_t *buf, int len)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct ftnandc021_chip *priv = chip->priv;
+	struct ftnandc021_regs *regs = priv->regs;
+	uint32_t tmp;
+
+	memset(buf, 0xff, len);
+
+	/* bad block */
+	buf[chip->badblockpos] = readl(&regs->bbird) & 0xff;
+
+	/* data */
+	tmp = readl(&regs->crcrd);
+	buf[8] = (tmp >> 0) & 0xff;
+	buf[9] = (tmp >> 8) & 0xff;
+	if (mtd->writesize >= 4096) {
+		buf[12] = (tmp >> 16) & 0xff;
+		buf[13] = (tmp >> 24) & 0xff;
+	}
+
+	tmp = readl(&regs->lsnrd);
+	buf[10] = (tmp >> 0) & 0xff;
+	buf[11] = (tmp >> 8) & 0xff;
+	if (mtd->writesize >= 4096) {
+		buf[14] = (tmp >> 16) & 0xff;
+		buf[15] = (tmp >> 24) & 0xff;
+	}
+}
+
+static void ftnandc021_set_oob(struct mtd_info *mtd,
+	const uint8_t *buf, int len)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct ftnandc021_chip *priv = chip->priv;
+	struct ftnandc021_regs *regs = priv->regs;
+	uint32_t tmp;
+
+	/* bad block */
+	tmp = buf[chip->badblockpos];
+	writel(tmp, &regs->bbiwr);
+
+	/* use 'W' to mark it as a non-blank page/block */
+	tmp = 'W' | (buf[9] << 8);
+	if (mtd->writesize > 2048)
+		tmp |= (buf[12] << 16) | (buf[13] << 24);
+	writel(tmp, &regs->crcwr);
+
+	tmp = buf[10] | (buf[11] << 8);
+	if (mtd->writesize > 2048)
+		tmp |= (buf[14] << 16) | (buf[15] << 24);
+	writel(tmp, &regs->lsnwr);
+}
+
+static uint8_t ftnandc021_read_byte(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct ftnandc021_chip *priv = chip->priv;
+	struct ftnandc021_regs *regs = priv->regs;
+	uint8_t ret = 0xff;
+
+	switch (priv->cmd) {
+	case NAND_CMD_READID:
+		if (priv->col < 8) {
+			uint32_t idx = priv->col / 4;
+			uint32_t pos = priv->col & 3;
+			uint32_t tmp = readl(&regs->idr[idx]);
+
+			ret = (uint8_t)(tmp >> (pos << 3));
+			priv->col += 1;
+		}
+		break;
+	case NAND_CMD_STATUS:
+		ret = (uint8_t)(readl(&regs->idr[1]) & 0xff);
+		break;
+	default:
+		printf("ftnandc021: bad cmd=0x%x in read_byte\n",
+			priv->cmd);
+		break;
+	}
+
+	return ret;
+}
+
+static uint16_t ftnandc021_read_word(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct ftnandc021_chip *priv = chip->priv;
+	struct ftnandc021_regs *regs = priv->regs;
+	uint16_t ret = 0xffff;
+
+	switch (priv->cmd) {
+	case NAND_CMD_READID:
+		if (priv->col < 8) {
+			uint32_t idx = priv->col / 4;
+			uint32_t pos = priv->col & 3;
+			uint32_t tmp = readl(&regs->idr[idx]);
+
+			ret = (uint16_t)(tmp >> (pos << 3));
+			priv->col += 2;
+		}
+		break;
+	case NAND_CMD_STATUS:
+		ret = (uint16_t)(readl(&regs->idr[1]) & 0xff);
+		break;
+	default:
+		printf("ftnandc021: bad cmd=0x%x in read_word\n",
+			priv->cmd);
+		break;
+	}
+
+	return ret;
+}
+
+/**
+ * Read data from NAND controller into buffer
+ * @mtd: MTD device structure
+ * @buf: buffer to store date
+ * @len: number of bytes to read
+ */
+static void ftnandc021_read_buf(struct mtd_info *mtd,
+	uint8_t *buf, int len)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct ftnandc021_chip *priv = chip->priv;
+	struct ftnandc021_regs *regs = priv->regs;
+	uint32_t off, val;
+
+	if (priv->col >= mtd->writesize)
+		return;
+
+	if (priv->cmd == NAND_CMD_READOOB)
+		BUG();	/* should never happen */
+
+	/* skip if it's a blank page */
+	if (chip->oob_poi[8] != 'W') {
+		memset(buf, 0xff, len);
+		return;
+	}
+
+	off = 0;
+	while (off < len && priv->col < mtd->writesize) {
+		ftnandc021_pio_wait(priv);
+		val = readl(&regs->dr);
+		memcpy(buf + off, &val, 4);
+		priv->col += 4;
+		off += 4;
+	}
+
+	ftnandc021_wait(priv);
+}
+
+/**
+ * Write buffer to NAND controller
+ * @mtd: MTD device structure
+ * @buf: data buffer
+ * @len: number of bytes to write
+ */
+static void ftnandc021_write_buf(struct mtd_info *mtd,
+	const uint8_t *buf, int len)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct ftnandc021_chip *priv = chip->priv;
+	struct ftnandc021_regs *regs = priv->regs;
+	uint32_t off, val;
+
+	/*
+	 * FTNANDC021 HW design issues:
+	 *
+	 * 1. OOB data must be set before issuing write command,
+	 *    so it's too late to do it right here
+	 * 2. Only after command issued, the data register
+	 *    could accept data.
+	 */
+	if (priv->col >= mtd->writesize)
+		return;
+
+	for (off = 0; off < len && priv->col < mtd->writesize; ) {
+		ftnandc021_pio_wait(priv);
+		memcpy(&val, buf + off, 4);
+		writel(val, &regs->dr);
+		priv->col += 4;
+		off += 4;
+	}
+
+	ftnandc021_wait(priv);
+}
+
+/**
+ * Verify chip data against buffer
+ * @mtd: MTD device structure
+ * @buf: buffer containing the data to compare
+ * @len: number of bytes to compare
+ */
+static int ftnandc021_verify_buf(struct mtd_info *mtd,
+	const uint8_t *buf, int len)
+{
+	int ret = 0;
+	uint8_t *tmp;
+
+	len = min_t(int, len, mtd->writesize);
+	tmp = malloc(mtd->writesize);
+
+	if (!tmp) {
+		printf("ftnandc021: out of memory\n");
+		return -ENOMEM;
+	} else {
+		ftnandc021_read_buf(mtd, tmp, len);
+		if (memcmp(tmp, buf, len))
+			ret = -EINVAL;
+	}
+
+	free(tmp);
+	return ret;
+}
+
+static void ftnandc021_cmdfunc(struct mtd_info *mtd,
+	unsigned cmd, int col, int page)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct ftnandc021_chip *priv = chip->priv;
+	struct ftnandc021_regs *regs = priv->regs;
+
+	priv->cmd = cmd;
+	priv->col = col;
+	priv->row = page;
+
+	switch (cmd) {
+	case NAND_CMD_READID:	/* 0x90 */
+		priv->col = 0;
+		ftnandc021_command(priv, FTNANDC021_CMD_RDID);
+		break;
+
+	case NAND_CMD_READOOB:	/* 0x50 */
+		priv->col = mtd->writesize;
+		/* fall-through */
+	case NAND_CMD_READ0:	/* 0x00 */
+		writel(page, &regs->pir);
+		writel(1, &regs->pcr);
+		/* get oob so that we cound do blank check later */
+		ftnandc021_command(priv, FTNANDC021_CMD_RDOOB);
+		ftnandc021_get_oob(mtd, chip->oob_poi, mtd->oobsize);
+		/* skip if we don't need page data */
+		if (priv->col >= mtd->writesize)
+			break;
+		/* skip if it's a blank page */
+		if (chip->oob_poi[8] != 'W') {
+			debug("ftnandc021: skip page %d\n", page);
+			break;
+		}
+		ftnandc021_command(priv, FTNANDC021_CMD_RDPG);
+		break;
+
+	case NAND_CMD_ERASE1:	/* 0x60 */
+		writel(page, &regs->pir);
+		writel(1, &regs->pcr);
+		break;
+
+	case NAND_CMD_ERASE2:	/* 0xD0 */
+		ftnandc021_command(priv, FTNANDC021_CMD_ERBLK);
+		break;
+
+	case NAND_CMD_STATUS:	/* 0x70 */
+		ftnandc021_command(priv, FTNANDC021_CMD_RDST);
+		break;
+
+	case NAND_CMD_SEQIN:	/* 0x80 (Write Stage 1.) */
+		writel(page, &regs->pir);
+		writel(1, &regs->pcr);
+		/* OOB data must be set before issuing command */
+		ftnandc021_set_oob(mtd, chip->oob_poi, mtd->oobsize);
+		if (priv->col >= mtd->writesize)
+			ftnandc021_command(priv, FTNANDC021_CMD_WROOB);
+		else
+			ftnandc021_command(priv, FTNANDC021_CMD_WRPG);
+		break;
+
+	case NAND_CMD_PAGEPROG:	/* 0x10 (Write Stage 2.) */
+		/* nothing needs to be done */
+		break;
+
+	case NAND_CMD_RESET:	/* 0xFF */
+		ftnandc021_command(priv, FTNANDC021_CMD_RESET);
+		break;
+
+	default:
+		printf("ftnandc021: unknown cmd=0x%x\n", cmd);
+	}
+}
+
+/**
+ * hardware specific access to control-lines
+ * @mtd: MTD device structure
+ * @cmd: command to device
+ * @ctrl:
+ * NAND_NCE: bit 0 -> don't care
+ * NAND_CLE: bit 1 -> Command Latch
+ * NAND_ALE: bit 2 -> Address Latch
+ *
+ * NOTE: boards may use different bits for these!!
+ */
+static void ftnandc021_hwcontrol(struct mtd_info *mtd,
+	int cmd, unsigned int ctrl)
+{
+	/* nothing needs to be done */
+}
+
+static int ftnandc021_reset(struct nand_chip *chip)
+{
+	struct ftnandc021_chip *priv = chip->priv;
+	struct ftnandc021_regs *regs = priv->regs;
+
+#ifdef CONFIG_SYS_FTNANDC021_TIMING
+	uint32_t timing[] = CONFIG_SYS_FTNANDC021_TIMING;
+
+	writel(timing[0], &regs->atr[0]);
+	writel(timing[1], &regs->atr[1]);
+#endif
+
+	writel(0, &regs->ier);
+	writel(0, &regs->pir);
+	writel(0xff, &regs->bbiwr);
+	writel(0xffffffff, &regs->lsnwr);
+	writel(0xffffffff, &regs->crcwr);
+
+	if (chip->options & NAND_BUSWIDTH_16)
+		writel(FCR_SWCRC | FCR_IGNCRC | FCR_16BIT, &regs->fcr);
+	else
+		writel(FCR_SWCRC | FCR_IGNCRC, &regs->fcr);
+
+	/* chip reset */
+	writel(SRR_CHIP_RESET | SRR_ECC_EN, &regs->srr);
+	while (readl(&regs->srr) & SRR_CHIP_RESET)
+		/* nothing to do */;
+
+	/* pio mode */
+	writel(0, &regs->bcr);
+
+	/* reset the underlying flash */
+	ftnandc021_command(priv, FTNANDC021_CMD_RESET);
+
+	return 0;
+}
+
+int ftnandc021_init(struct nand_chip *chip, uint32_t mmio)
+{
+	struct mtd_info *mtd = &nand_info[0];
+	struct ftnandc021_chip *priv;
+	struct ftnandc021_regs *regs = (void __iomem *)mmio;
+	uint32_t bk, pg, ac, alen;
+
+	priv = calloc(1, sizeof(struct ftnandc021_chip));
+	if (!priv)
+		return -ENOMEM;
+
+	priv->mtd = mtd;
+	priv->regs = regs;
+
+	chip->priv = priv;
+
+	/* hwcontrol is mandatory */
+	chip->cmd_ctrl   = ftnandc021_hwcontrol;
+	chip->cmdfunc    = ftnandc021_cmdfunc;
+	chip->dev_ready  = ftnandc021_dev_ready;
+	chip->chip_delay = 0;
+
+	chip->read_byte  = ftnandc021_read_byte;
+	chip->read_word  = ftnandc021_read_word;
+	chip->read_buf   = ftnandc021_read_buf;
+	chip->write_buf  = ftnandc021_write_buf;
+	chip->verify_buf = ftnandc021_verify_buf;
+
+	chip->ecc.read_page      = ftnandc021_read_page;
+	chip->ecc.write_page     = ftnandc021_write_page;
+	chip->ecc.read_page_raw  = ftnandc021_read_page_raw;
+	chip->ecc.write_page_raw = ftnandc021_write_page_raw;
+
+	/* hardware reset */
+	if (ftnandc021_reset(chip))
+		return -EINVAL;
+
+	/* Detect NAND chips */
+	if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL))
+		return -ENXIO;
+
+	/* Setup NAND flash parameters */
+	alen = (mtd->writesize < 2048) ? 1 : 2;
+	if (lldiv(mtd->size, mtd->writesize) > 0x10000)
+		alen += 3;
+	else if (lldiv(mtd->size, mtd->writesize) > 0x100)
+		alen += 2;
+	else
+		alen += 1;
+
+	debug("ftnandc021: pg=%dK, bk=%dK, alen=%d\n",
+		mtd->writesize >> 10, mtd->erasesize >> 10, alen);
+
+	/* Sanity checks */
+	switch (mtd->writesize) {
+	case 512:
+	case 2048:
+	case 4096:
+		break;
+	default:
+		printf("ftnandc021: %d bytes per page is not supported\n",
+			mtd->writesize);
+		return -EINVAL;
+	}
+
+	/* Update hardware register */
+	bk = ffs(mtd->erasesize / mtd->writesize) - 5;
+	pg = (mtd->writesize < 2048) ? 0 : (ffs(mtd->writesize) - 11);
+	ac = alen - 3;
+	writel(MCR_ME(0) | MCR_32GB | (bk << 16) | (pg << 8) | (ac << 10),
+		&regs->mcr);
+
+	/* Update ECC parameters */
+	chip->ecc.mode = NAND_ECC_HW;
+	chip->ecc.size = mtd->writesize;
+	chip->ecc.steps = 1;
+	chip->ecc.strength = CFGR_ECC_BITS(readl(&regs->cfgr));
+	if (mtd->writesize > 2048)
+		chip->ecc.layout = &nand_4k_ecclayout;
+	else
+		chip->ecc.layout = &nand_ecclayout;
+
+	/* Finish the scan process */
+	if (nand_scan_tail(mtd))
+		return -ENXIO;
+
+	return 0;
+}
diff --git a/drivers/mtd/nand/ftnandc021_spl.c b/drivers/mtd/nand/ftnandc021_spl.c
new file mode 100644
index 0000000..9f84a98
--- /dev/null
+++ b/drivers/mtd/nand/ftnandc021_spl.c
@@ -0,0 +1,203 @@
+/*
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. <http://www.faraday-tech.com/tw/>
+ * Kuo-Jung Su <dantesu@gmail.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <spl.h>
+#include <faraday/ftnandc021.h>
+
+#define CFG_CMD_TIMEOUT     200
+
+struct ftnandc021_chip {
+	struct ftnandc021_regs *regs;
+	int bits;
+	int alen;
+	int page_shift;
+	int block_shift;
+};
+
+static struct ftnandc021_chip this_chip = {
+	.regs = (void __iomem *)CONFIG_SYS_NAND_BASE,
+	.bits = 8,
+	.alen = 4,
+	.page_shift = 11,  /* 2KB page */
+	.block_shift = 17, /* 128KB block */
+};
+
+static struct ftnandc021_chip *chip = &this_chip;
+
+static int ftnandc021_wait(void)
+{
+	struct ftnandc021_regs *regs = chip->regs;
+	int ret = -1;
+	ulong ts;
+
+	for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
+		if (readl(&regs->sr) & SR_ECC) {
+			ret = -2;
+			break;
+		}
+		if (!(readl(&regs->acr) & ACR_START)) {
+			ret = 0;
+			break;
+		}
+	}
+
+	switch (ret) {
+	case -2:
+		puts("ecc failed\n");
+		break;
+	case -1:
+		puts("cmd timeout\n");
+		break;
+	default:
+		break;
+	}
+
+	return ret;
+}
+
+static int ftnandc021_command(uint32_t page, uint32_t cmd)
+{
+	struct ftnandc021_regs *regs = chip->regs;
+	int ret = 0;
+
+	writel(1, &regs->pcr);
+	writel(page, &regs->pir);
+	writel(ACR_START | ACR_CMD(cmd), &regs->acr);
+
+	if (cmd != FTNANDC021_CMD_RDPG)
+		ret = ftnandc021_wait();
+
+	return ret;
+}
+
+static int ftnandc021_bad_block(uint32_t off)
+{
+	struct ftnandc021_regs *regs = chip->regs;
+	uint32_t block_mask = (1 << chip->block_shift) - 1;
+	uint32_t page = (off & ~block_mask) >> chip->page_shift;
+
+	if (ftnandc021_command(page, FTNANDC021_CMD_RDOOB))
+		return 1;
+
+	if ((readl(&regs->bbird) & 0xff) != 0xff)
+		return 1;
+
+	return 0;
+}
+
+static void ftnandc021_reset(void)
+{
+	struct ftnandc021_regs *regs = chip->regs;
+	uint32_t bk, pg, ac;
+
+	/* chip reset */
+	writel(SRR_CHIP_RESET | SRR_ECC_EN, &regs->srr);
+	while ((readl(&regs->srr) & SRR_CHIP_RESET))
+		/* nothing to do */;
+	writel(0, &regs->ier);
+	writel(0, &regs->pir);
+	writel(0xff, &regs->bbiwr);
+	writel(0xffffffff, &regs->lsnwr);
+	writel(0xffffffff, &regs->crcwr);
+
+	/* bus width */
+	if (chip->bits > 8)
+		writel(FCR_SWCRC | FCR_IGNCRC | FCR_16BIT, &regs->fcr);
+	else
+		writel(FCR_SWCRC | FCR_IGNCRC, &regs->fcr);
+
+	/* pio mode */
+	writel(0, &regs->bcr);
+
+	/* NAND flash configuration */
+	ac = chip->alen - 3;
+	bk = chip->block_shift - chip->page_shift - 4;
+	pg = (chip->page_shift <= 9) ? 0 : (chip->page_shift - 10);
+	writel(MCR_ME(0) | MCR_32GB | (bk << 16) | (pg << 8) | (ac << 10),
+		&regs->mcr);
+}
+
+/* nand_init() - initialize data to make nand usable by SPL */
+void nand_init(void)
+{
+	struct spl_flash_info *info = &spl_flash;
+
+	chip->alen = info->col_adrc + info->row_adrc;
+	chip->bits = info->bits;
+	chip->page_shift = info->pg_shift;
+	chip->block_shift = info->bk_shift;
+
+	ftnandc021_reset();
+}
+
+/* Unselect after operation */
+void nand_deselect(void)
+{
+	ftnandc021_reset();
+}
+
+int nand_spl_load_image(uint32_t off, unsigned int len, void *dst)
+{
+	struct ftnandc021_regs *regs = chip->regs;
+	uint32_t page_mask = (1 << chip->page_shift) - 1;
+	uint32_t block_mask = (1 << chip->block_shift) - 1;
+	uint32_t i, w;
+	uint8_t *pw = (uint8_t *)&w;
+	uint8_t *buf = dst;
+
+	if ((off & page_mask) || (len & 3)) {
+		puts("nand: bad offset or length\n");
+		return -1;
+	}
+
+	while (len > 0) {
+		/* skip bad block */
+		if (ftnandc021_bad_block(off)) {
+			off += 1 << chip->block_shift;
+			continue;
+		}
+		/* block read */
+		do {
+			/* page read */
+			if (ftnandc021_command(
+				off >> chip->page_shift, FTNANDC021_CMD_RDPG))
+				return -1;
+
+			for (i = 0; i < (1 << chip->page_shift); i += 4) {
+				/* pio wait */
+				while (!(readl(&regs->ior) & 1))
+					;
+				/* pio read */
+				w = readl(&regs->dr);
+				if (len > 0) {
+					/* alignment safe */
+					buf[0] = pw[0];
+					buf[1] = pw[1];
+					buf[2] = pw[2];
+					buf[3] = pw[3];
+					/* advance the pointer */
+					buf += 4;
+					len -= 4;
+				}
+			}
+
+			/* wait until command finished */
+			if (ftnandc021_wait())
+				return -1;
+
+			off += 1 << chip->page_shift;
+
+		} while (len > 0 && (off & block_mask));
+	}
+
+	return 0;
+}
diff --git a/include/faraday/ftnandc021.h b/include/faraday/ftnandc021.h
new file mode 100644
index 0000000..2caebb6
--- /dev/null
+++ b/include/faraday/ftnandc021.h
@@ -0,0 +1,151 @@
+/*
+ * Faraday NAND Flash Controller
+ *
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. <http://www.faraday-tech.com/tw/>
+ * Kuo-Jung Su <dantesu@gmail.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __FTNANDC021_H
+#define __FTNANDC021_H
+
+/* NANDC control registers */
+struct ftnandc021_regs {
+	/* 0x000 ~ 0x0fc */
+	uint32_t ecc_pr[4];/* ECC Parity Register */
+	uint32_t ecc_sr;   /* ECC Status Register */
+	uint32_t rsvd0[59];
+
+	/* 0x100 ~ 0x1fc */
+	uint32_t sr;	 /* Status Register */
+	uint32_t acr;	 /* Access Control Register */
+	uint32_t fcr;	 /* Flow Control Register */
+	uint32_t pir;	 /* Page Index Register */
+	uint32_t mcr;	 /* Memory Configuration Register */
+	uint32_t atr[2]; /* AC Timing Register */
+	uint32_t rsvd1[1];
+	uint32_t idr[2]; /* Device ID Register */
+	uint32_t ier;	 /* Interrupt Enable Register */
+	uint32_t iscr;	 /* Interrupt Status Clear Register */
+	uint32_t rsvd2[4];
+	uint32_t bbiwr;	 /* Bad Block Info Write */
+	uint32_t lsn;	 /* LSN Initialize */
+	uint32_t crcwr;	 /* LSN CRC Write */
+	uint32_t lsnwr;	 /* LSN Write */
+	uint32_t bbird;	 /* Bad Block Info Read */
+	uint32_t lsnrd;	 /* LSN Read */
+	uint32_t crcrd;	 /* CRC Read */
+	uint32_t rsvd3[41];
+
+	/* 0x200 ~ 0x2fc */
+	uint32_t rsvd4[1];
+	uint32_t icr;	 /* BMC Interrupt Control Register */
+	uint32_t ior;	 /* BMC PIO Status Register */
+	uint32_t bcr;	 /* BMC Burst Control Register */
+	uint32_t rsvd5[60];
+
+	/* 0x300 ~ 0x3fc */
+	uint32_t dr;	 /* MLC Data Register */
+	uint32_t isr;	 /* MLC Interrupt Status Register */
+	uint32_t pcr;	 /* Page Count Register */
+	uint32_t srr;	 /* MLC Software Reset Register */
+	uint32_t rsvd7[58];
+	uint32_t revr;	 /* Revision Register */
+	uint32_t cfgr;	 /* Configuration Register */
+};
+
+/* ECC Status Register */
+#define ECC_SR_CERR      (1 << 3)  /* correction error */
+#define ECC_SR_ERR       (1 << 2)  /* ecc error */
+#define ECC_SR_DEC       (1 << 1)  /* ecc decode finished */
+#define ECC_SR_ENC       (1 << 0)  /* ecc encode finished */
+
+/* Status Register */
+#define SR_BLANK         (1 << 7)  /* blanking check failed */
+#define SR_ECC           (1 << 6)  /* ecc timeout */
+#define SR_STS           (1 << 4)  /* status error */
+#define SR_CRC           (1 << 3)  /* crc error */
+#define SR_CMD           (1 << 2)  /* command finished */
+#define SR_READY         (1 << 1)  /* chip ready/busy */
+#define SR_ENA           (1 << 0)  /* chip enabled */
+
+/* Access Control Register */
+#define ACR_CMD(x)       (((x) & 0x1f) << 8) /* command code */
+#define ACR_START        (1 << 7)  /* command start */
+
+/* Flow Control Register */
+#define FCR_SWCRC        (1 << 8)  /* CRC controlled by Software */
+#define FCR_IGNCRC       (1 << 7)  /* Bypass/Ignore CRC checking */
+#define FCR_16BIT        (1 << 4)  /* 16 bit data bus */
+#define FCR_WPROT        (1 << 3)  /* write protected */
+#define FCR_NOSC         (1 << 2)  /* bypass status check error */
+#define FCR_MICRON       (1 << 1)  /* Micron 2-plane command */
+#define FCR_NOBC         (1 << 0)  /* skip blanking check error */
+
+/* Interrupt Enable Register */
+#define IER_ENA          (1 << 7)  /* interrupt enabled */
+#define IER_ECC          (1 << 3)  /* ecc error timeout */
+#define IER_STS          (1 << 2)  /* status error */
+#define IER_CRC          (1 << 1)  /* crc error */
+#define IER_CMD          (1 << 0)  /* command finished */
+
+/* BMC PIO Status Register */
+#define IOR_READY        (1 << 0)  /* PIO ready */
+
+/* MLC Software Reset Register */
+#define SRR_ECC_EN       (1 << 8)  /* ECC enabled */
+#define SRR_NANDC_RESET  (1 << 2)  /* NANDC reset */
+#define SRR_BMC_RESET    (1 << 1)  /* BMC reset */
+#define SRR_ECC_RESET    (1 << 0)  /* ECC reset */
+#define SRR_CHIP_RESET   (SRR_NANDC_RESET | SRR_BMC_RESET | SRR_ECC_RESET)
+
+/* Memory Configuration Register */
+#define MCR_BS16P        (0 << 16) /* page count per block */
+#define MCR_BS32P        (1 << 16)
+#define MCR_BS64P        (2 << 16)
+#define MCR_BS128P       (3 << 16)
+#define MCR_1PLANE       (0 << 14) /* memory architecture */
+#define MCR_2PLANE       (1 << 14)
+#define MCR_SERIAL       (0 << 12) /* interleaving: off, 2 flash, 4 flash */
+#define MCR_IL2          (1 << 12)
+#define MCR_IL4          (2 << 12)
+#define MCR_ALEN3        (0 << 10) /* address length */
+#define MCR_ALEN4        (1 << 10)
+#define MCR_ALEN5        (2 << 10)
+#define MCR_PS512        (0 << 8)  /* size per page (bytes) */
+#define MCR_PS2048       (1 << 8)
+#define MCR_PS4096       (2 << 8)
+#define MCR_16MB         (0 << 4)  /* flash size */
+#define MCR_32MB         (1 << 4)
+#define MCR_64MB         (2 << 4)
+#define MCR_128MB        (3 << 4)
+#define MCR_256MB        (4 << 4)
+#define MCR_512MB        (5 << 4)
+#define MCR_1GB          (6 << 4)
+#define MCR_2GB          (7 << 4)
+#define MCR_4GB          (8 << 4)
+#define MCR_8GB          (9 << 4)
+#define MCR_16GB         (10 << 4)
+#define MCR_32GB         (11 << 4)
+#define MCR_ME(n)        (1 << (n)) /* module enable, 0 <= n <= 3 */
+
+/* Configuration Register */
+#define CFGR_ECC_BITS(x)     (((x) >> 16) & 0x0f) /* 4 or 8 */
+#define CFGR_BUS_WIDTH(x)    (((x) >> 8) & 0xff) /* 8 or 16 */
+#define CFGR_MAX_MODULE(x)   ((x) & 0x0f) /* max. module(flash) */
+
+/* FTNANDC021 built-in command set */
+#define FTNANDC021_CMD_RDID  0x01   /* read id */
+#define FTNANDC021_CMD_RESET 0x02   /* reset flash */
+#define FTNANDC021_CMD_RDST  0x04   /* read status */
+#define FTNANDC021_CMD_RDPG  0x05   /* read page (data + oob) */
+#define FTNANDC021_CMD_RDOOB 0x06   /* read oob */
+#define FTNANDC021_CMD_WRPG  0x10   /* write page (data + oob) */
+#define FTNANDC021_CMD_ERBLK 0x11   /* erase block */
+#define FTNANDC021_CMD_WROOB 0x13   /* write oob */
+
+int ftnandc021_init(struct nand_chip *chip, uint32_t mmio);
+
+#endif /* EOF */
--
1.7.9.5