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From: Prabhakar Kushwaha <prabhakar@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH][v2] board/t1040qds: Enable memory reset control
Date: Thu, 26 Dec 2013 12:40:55 +0530	[thread overview]
Message-ID: <1388041856-4083-1-git-send-email-prabhakar@freescale.com> (raw)

Define QIXIS_RST_FORCE_MEM to reset on-board DDR-DIMM before start
accessing it. 

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
 Changes for v2: Incorporated York's comments
	- Update subject and description

 board/freescale/t1040qds/t1040qds.c |    5 +++++
 include/configs/T1040QDS.h          |    1 +
 2 files changed, 6 insertions(+)

diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c
index 2aa176c..de3ea5c 100644
--- a/board/freescale/t1040qds/t1040qds.c
+++ b/board/freescale/t1040qds/t1040qds.c
@@ -239,3 +239,8 @@ void qixis_dump_switch(void)
 		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 	}
 }
+
+int board_need_mem_reset(void)
+{
+	return 1;
+}
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 1cfbf06..7bae2c8 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -232,6 +232,7 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define	QIXIS_RST_FORCE_MEM		0x01
 
 #define CONFIG_SYS_CSPR3_EXT	(0xf)
 #define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
-- 
1.7.9.5

             reply	other threads:[~2013-12-26  7:10 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-12-26  7:10 Prabhakar Kushwaha [this message]
2014-01-03  0:00 ` [U-Boot] [PATCH][v2] board/t1040qds: Enable memory reset control York Sun

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