[U-Boot] [PATCH 4/6] module enabler cleanup.

[Yoshinori Sato <ysato@users.sourceforge.jp>]

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
 arch/sh/cpu/sh2/cpu.c          | 27 ++++++++++++---------------
 arch/sh/include/asm/cpu_sh2.h  |  4 +++-
 arch/sh/include/asm/cpu_sh2a.h | 19 +++++++++++++++++++
 3 files changed, 34 insertions(+), 16 deletions(-)
 create mode 100644 arch/sh/include/asm/cpu_sh2a.h

diff --git a/arch/sh/cpu/sh2/cpu.c b/arch/sh/cpu/sh2/cpu.c
index b401d08..0a6a58b 100644
--- a/arch/sh/cpu/sh2/cpu.c
+++ b/arch/sh/cpu/sh2/cpu.c
@@ -10,16 +10,17 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 
-#define STBCR4      0xFFFE040C
-#define cmt_clock_enable() do {\
-		writeb(readb(STBCR4) & ~0x04, STBCR4);\
-	} while (0)
-#define scif0_enable() do {\
-		writeb(readb(STBCR4) & ~0x80, STBCR4);\
-	} while (0)
-#define scif3_enable() do {\
-		writeb(readb(STBCR4) & ~0x10, STBCR4);\
-	} while (0)
+#if defined(CONFIG_CONS_SCIF0)
+# define CH 0
+#elif defined(CONFIG_CONS_SCIF1)
+# define CH 1
+#elif defined(CONFIG_CONS_SCIF2)
+# define CH 2
+#elif defined(CONFIG_CONS_SCIF3)
+# define CH 3
+#else
+# error "Default SCIF doesn't set....."
+#endif
 
 int checkcpu(void)
 {
@@ -30,11 +31,7 @@ int checkcpu(void)
 int cpu_init(void)
 {
 	/* SCIF enable */
-#if defined(CONFIG_CONS_SCIF3)
-	scif3_enable();
-#else
-	scif0_enable();
-#endif
+	scif_enable(CH);
 	/* CMT clock enable */
 	cmt_clock_enable() ;
 	return 0;
diff --git a/arch/sh/include/asm/cpu_sh2.h b/arch/sh/include/asm/cpu_sh2.h
index b67c093..62b5179 100644
--- a/arch/sh/include/asm/cpu_sh2.h
+++ b/arch/sh/include/asm/cpu_sh2.h
@@ -8,7 +8,9 @@
 #ifndef _ASM_CPU_SH2_H_
 #define _ASM_CPU_SH2_H_
 
-
+#if defined(CONFIG_SH2A)
+#  include <asm/cpu_sh2a.h>
+#endif
 #if defined(CONFIG_CPU_SH7203)
 # include <asm/cpu_sh7203.h>
 #elif defined(CONFIG_CPU_SH7264)
diff --git a/arch/sh/include/asm/cpu_sh2a.h b/arch/sh/include/asm/cpu_sh2a.h
new file mode 100644
index 0000000..6de9729
--- /dev/null
+++ b/arch/sh/include/asm/cpu_sh2a.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_CPU_SH2A_H_
+#define _ASM_CPU_SH2A_H_
+
+/* module enable */
+#define STBCR4		0xFFFE040C
+#define scif_enable(ch)					 \
+do { 							 \
+	if (ch < 4) { 					 \
+		unsigned char mask = 1 << (7 - ch); 			 \
+		writeb((readb(STBCR4) & ~mask), STBCR4); \
+	} 						 \
+} while (0)
+
+#define cmt_clock_enable() \
+do { 							 \
+		writeb((readb(STBCR4) & ~0x04), STBCR4); \
+} while (0)
+
+#endif
-- 
1.8.5.3