* [U-Boot] [PATCH v2 1/6] Add MS7206SE support
2014-02-13 14:13 [U-Boot] [PATCH v2 0/6] Add target board MS7206SE Yoshinori Sato
@ 2014-02-13 14:13 ` Yoshinori Sato
2014-02-13 14:13 ` [U-Boot] [PATCH v2 2/6] Add MS7206SE ethernet support Yoshinori Sato
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Yoshinori Sato @ 2014-02-13 14:13 UTC (permalink / raw)
To: u-boot
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
board/renesas/ms7206se/Makefile | 10 +++
board/renesas/ms7206se/lowlevel_init.S | 124 +++++++++++++++++++++++++++++++++
board/renesas/ms7206se/ms7206se.c | 43 ++++++++++++
boards.cfg | 1 +
include/configs/ms7206se.h | 95 +++++++++++++++++++++++++
5 files changed, 273 insertions(+)
create mode 100644 board/renesas/ms7206se/Makefile
create mode 100644 board/renesas/ms7206se/lowlevel_init.S
create mode 100644 board/renesas/ms7206se/ms7206se.c
create mode 100644 include/configs/ms7206se.h
diff --git a/board/renesas/ms7206se/Makefile b/board/renesas/ms7206se/Makefile
new file mode 100644
index 0000000..eed3769
--- /dev/null
+++ b/board/renesas/ms7206se/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2013 Yoshinori Sato <ysato@users.sourceforge.jp>
+#
+# u-boot/board/renesas/ms7206se/Makefile
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ms7206se.o
+obj-y += lowlevel_init.o
diff --git a/board/renesas/ms7206se/lowlevel_init.S b/board/renesas/ms7206se/lowlevel_init.S
new file mode 100644
index 0000000..4e5bde4
--- /dev/null
+++ b/board/renesas/ms7206se/lowlevel_init.S
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2013 Yoshinori Sato <ysato@users.sourceforge.jp>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+#include <asm/macro.h>
+#define INTMSK0 0x11800000
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+ mova CPG_settings_table,r0
+1: mov.l @r0+,r3 // Address (or zero)
+ tst r3,r3
+ bt 2f
+ mov.l @r0+,r1 // data
+ bra 1b
+ mov.w r1, at r3
+2:
+ mov.l $mclkcr,r0 // MCLKCR setting
+ mov #0x40,r1
+ mov.b r1, at r0
+
+ // Set up the Bus Controler
+ mova BSC_settings_table,r0
+5: mov.l @r0+,r3 // Address (or zero)
+ tst r3,r3
+ bt 6f
+ mov.l @r0+,r1 // data
+ bra 5b
+ mov.l r1, at r3
+
+6:
+ mov.l $delay_count,r0
+7:
+ dt r0
+ bf 7b
+
+ mov.l $SDMR,r1 // Turns on SDRAM controller
+ mov.l $SDMR_val,r2
+ mov.l r2, at r1
+
+ // Set up the Pin Function Controler
+ mova PFC_settings_table,r0
+3: mov.l @r0+,r3 // Address (or zero)
+ tst r3,r3
+ bt 4f
+ mov.l @r0+,r1 // data
+ bra 3b
+ mov.w r1, at r3
+4:
+ rts/n
+
+ .align 4
+$delay_count:
+ .long 2000
+$SDMR: .long 0xfffc5880
+$SDMR_val:
+ .long 0
+
+$mclkcr:
+ .long MCLKCR
+
+CPG_settings_table:
+ .long WTCSR,0xA500
+ .long WTCNT,0x5A00
+ .long WTCSR,0xA51E
+ .long FRQCR, 0x120c /* input:33.3333MHz I:B:P=6:2:1=200MHz:66MHz:33MHz */
+ .long 0
+
+BSC_settings_table:
+ # Settings from Hitachi docs for SE7206
+ .long CMNCR, 0x00001010
+ .long CS0BCR, 0x10000600
+ .long CS2BCR, 0x10000600
+ .long CS4BCR, 0x10000400
+ .long CS5BCR, 0x10000400
+ .long CS3BCR, 0x10004600
+ .long CS0WCR, 0x00000380 /* wait:4cycle */
+ .long CS2WCR, 0x00000380
+ .long CS4WCR, 0x00000380
+ .long CS5WCR, 0x00000380
+ .long CS3WCR, 0x00004892 /* pre->actv:1cycle, actv->read/write:2cycle, write->pre:1cycle, ref->actv:4cycle */
+ .long SDCR, 0x00000811
+ .long RTCNT, 0xa55a0083
+ .long RTCOR, 0xa55a0083
+ .long RTCSR, 0xa55a0008 /* reflesh count=Bclk/4 */
+ .long 0
+
+PFC_settings_table:
+ .long PACRH3, 0x0022
+ .long PACRH2, 0x1111
+ .long PACRH1, 0x1115
+ .long PACRL4, 0x1111
+ .long PACRL3, 0x1125
+ .long PACRL2, 0x2255
+ .long PACRL1, 0x5500
+ .long PBCR3, 0x0022
+ .long PBCR2, 0x2244
+ .long PBCR1, 0x1111
+ .long PCCRL1, 0x1111
+ .long PDCRH4, 0x1111
+ .long PDCRH3, 0x1111
+ .long PDCRH2, 0x1111
+ .long PDCRH1, 0x1111
+ .long PDCRL4, 0x1111
+ .long PDCRL3, 0x1111
+ .long PECRH1, 0x0005
+ .long PECRL4, 0x3223
+ .long PECRL3, 0x3030
+ .long PECRL2, 0x3550
+ .long IFCR, 0x0003
+ .long 0
+
+$INTMSK0:
+ .long INTMSK0
diff --git a/board/renesas/ms7206se/ms7206se.c b/board/renesas/ms7206se/ms7206se.c
new file mode 100644
index 0000000..45906fb
--- /dev/null
+++ b/board/renesas/ms7206se/ms7206se.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2013 Yoshinori Sato <ysato@users.sourceforge.jp>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("BOARD: Renesas Technology MS7206SE\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/boards.cfg b/boards.cfg
index c97c4bd..a56f196 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -1203,6 +1203,7 @@ Active powerpc ppc4xx - xilinx ppc440-generic
Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic_flash xilinx-ppc440-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda@uam.es>
Active sandbox sandbox - sandbox sandbox sandbox - Simon Glass <sjg@chromium.org>
Active sh sh2 - renesas rsk7203 rsk7203 - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Active sh sh2 - renesas ms7206se ms7206se - Yoshinori Sato <ysato@users.sourceforge.jp>
Active sh sh2 - renesas rsk7264 rsk7264 - Phil Edworthy <phil.edworthy@renesas.com>
Active sh sh2 - renesas rsk7269 rsk7269 - -
Active sh sh3 - - mpr2 mpr2 - Mark Jonas <mark.jonas@de.bosch.com>
diff --git a/include/configs/ms7206se.h b/include/configs/ms7206se.h
new file mode 100644
index 0000000..805044c
--- /dev/null
+++ b/include/configs/ms7206se.h
@@ -0,1 +1,95 @@
+/*
+ * Configuation settings for the Renesas Technology MS7206SE
+ *
+ * Copyright (C) 2013 Yoshinori Sato <ysato@users.sourceforge.jp>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MS7206SE_H
+#define __MS7206SE
+
+#undef DEBUG
+#define CONFIG_SH 1
+#define CONFIG_SH2 1
+#define CONFIG_SH2A 1
+#define CONFIG_CPU_SH7206 1
+#define CONFIG_MS7206SE 1
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_CMD_CACHE
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTARGS "console=ttySC3,115200"
+#define CONFIG_LOADADDR 0x0C100000 /* MS7206SE01_SDRAM_BASE + 1MB */
+
+#define CONFIG_VERSION_VARIABLE
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+/* MEMORY */
+#define MS7206SE_SDRAM_BASE 0x0C000000
+#define MS7206SE_FLASH_BASE_1 0x20000000 /* Non cache */
+#define MS7206SE_FLASH_BANK_SIZE (16 * 1024 * 1024)
+
+#define CONFIG_SYS_TEXT_BASE 0x0C7C0000
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
+#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
+#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
+/* Buffer size for Boot Arguments passed to kernel */
+#define CONFIG_SYS_BARGSIZE 512
+/* List of legal baudrate settings for this board */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE 1
+#define CONFIG_CONS_SCIF3 1
+
+#define CONFIG_SYS_MEMTEST_START CONFIG_LOADADDR
+#define CONFIG_SYS_MEMTEST_END (CONFIG_LOADADDR + (63 * 1024 * 1024))
+
+#define CONFIG_SYS_SDRAM_BASE MS7206SE_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
+
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 1024 * 1024)
+#define CONFIG_SYS_MONITOR_BASE MS7206SE_FLASH_BASE_1
+#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#undef CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_BASE MS7206SE_FLASH_BASE_1
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_SECT 142
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_FLASH_ERASE_TOUT 12000
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ 33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
+#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
+
+/* Network interface */
+#define CONFIG_SMC91111
+#define CONFIG_SMC91111_BASE (0x30000000)
+
+#endif /* __MS7206SE_H */
--
1.8.5.3
^ permalink raw reply related [flat|nested] 8+ messages in thread* [U-Boot] [PATCH v2 2/6] Add MS7206SE ethernet support
2014-02-13 14:13 [U-Boot] [PATCH v2 0/6] Add target board MS7206SE Yoshinori Sato
2014-02-13 14:13 ` [U-Boot] [PATCH v2 1/6] Add MS7206SE support Yoshinori Sato
@ 2014-02-13 14:13 ` Yoshinori Sato
2015-01-30 21:29 ` Joe Hershberger
2014-02-13 14:13 ` [U-Boot] [PATCH v2 3/6] Add SH7206 support Yoshinori Sato
` (3 subsequent siblings)
5 siblings, 1 reply; 8+ messages in thread
From: Yoshinori Sato @ 2014-02-13 14:13 UTC (permalink / raw)
To: u-boot
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/net/smc91111.h | 31 ++++++++++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h
index 9deee9b..24b2b51 100644
--- a/drivers/net/smc91111.h
+++ b/drivers/net/smc91111.h
@@ -236,7 +236,36 @@ struct smc91111_priv{
*(__b2 + __i) = SMC_inb((a),(r)); \
}; \
}while(0)
-
+#elif defined(CONFIG_MS7206SE)
+#define SWAB7206(x) ({ word __x = x; ((__x << 8)|(__x >> 8)); })
+#define SMC_inw(a, r) *((volatile word*)((a)->iobase + (r)))
+#define SMC_inb(a, r) (*((volatile byte*)((a)->iobase + ((r) ^ 0x01))))
+#define SMC_insw(a, r, b, l) \
+ do { \
+ int __i; \
+ word *__b2 = (word *)(b); \
+ for (__i = 0; __i < (l); __i++) { \
+ *__b2++ = SWAB7206(SMC_inw(a, r)); \
+ } \
+ } while (0)
+#define SMC_outw(a, d, r) (*((volatile word *)((a)->iobase+(r))) = d)
+#define SMC_outb(a, d, r) ({ word __d = (byte)(d); \
+ word __w = SMC_inw((a), ((r)&(~1))); \
+ if (((r) & 1)) \
+ __w = (__w & 0x00ff) | (__d << 8); \
+ else \
+ __w = (__w & 0xff00) | (__d); \
+ SMC_outw((a), __w, ((r)&(~1))); \
+ })
+#define SMC_outsw(a, r, b, l) \
+ do { \
+ int __i; \
+ word *__b2 = (word *)(b); \
+ for (__i = 0; __i < (l); __i++) { \
+ SMC_outw(a, SWAB7206(*__b2), r); \
+ __b2++; \
+ } \
+ } while (0)
#else /* if not CONFIG_CPU_PXA25X and not CONFIG_LEON */
#ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */
--
1.8.5.3
^ permalink raw reply related [flat|nested] 8+ messages in thread* [U-Boot] [PATCH v2 3/6] Add SH7206 support
2014-02-13 14:13 [U-Boot] [PATCH v2 0/6] Add target board MS7206SE Yoshinori Sato
2014-02-13 14:13 ` [U-Boot] [PATCH v2 1/6] Add MS7206SE support Yoshinori Sato
2014-02-13 14:13 ` [U-Boot] [PATCH v2 2/6] Add MS7206SE ethernet support Yoshinori Sato
@ 2014-02-13 14:13 ` Yoshinori Sato
2014-02-13 14:13 ` [U-Boot] [PATCH v2 4/6] SH2A cache support Yoshinori Sato
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Yoshinori Sato @ 2014-02-13 14:13 UTC (permalink / raw)
To: u-boot
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/include/asm/cpu_sh2.h | 2 ++
arch/sh/include/asm/cpu_sh7206.h | 75 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 77 insertions(+)
create mode 100644 arch/sh/include/asm/cpu_sh7206.h
diff --git a/arch/sh/include/asm/cpu_sh2.h b/arch/sh/include/asm/cpu_sh2.h
index 18a0f0b..ca7b630 100644
--- a/arch/sh/include/asm/cpu_sh2.h
+++ b/arch/sh/include/asm/cpu_sh2.h
@@ -20,6 +20,8 @@
#if defined(CONFIG_CPU_SH7203)
# include <asm/cpu_sh7203.h>
+#elif defined(CONFIG_CPU_SH7206)
+# include <asm/cpu_sh7206.h>
#elif defined(CONFIG_CPU_SH7264)
# include <asm/cpu_sh7264.h>
#elif defined(CONFIG_CPU_SH7269)
diff --git a/arch/sh/include/asm/cpu_sh7206.h b/arch/sh/include/asm/cpu_sh7206.h
new file mode 100644
index 0000000..165b2f6
--- /dev/null
+++ b/arch/sh/include/asm/cpu_sh7206.h
@@ -0,0 +1,75 @@
+#ifndef _ASM_CPU_SH7206_H_
+#define _ASM_CPU_SH7206_H_
+
+/* Cache */
+#define CCR1 0xFFFC1000
+#define CCR2 0xFFFC1004
+#define CCR CCR1
+
+#define CMNCR 0xFFFC0000
+#define CS0BCR 0xFFFC0004
+#define CS2BCR 0xFFFC000C
+#define CS3BCR 0xFFFC0010
+#define CS4BCR 0xFFFC0014
+#define CS5BCR 0xFFFC0018
+#define CS0WCR 0xFFFC0028
+#define CS2WCR 0xFFFC0030
+#define CS3WCR 0xFFFC0034
+#define CS4WCR 0xFFFC0038
+#define CS5WCR 0xFFFC003C
+#define SDCR 0xFFFC004C
+#define RTCSR 0xFFFC0050
+#define RTCNT 0xFFFC0054
+#define RTCOR 0xFFFC0058
+
+/* SCIF */
+#define SCSMR_0 0xFFFE8000
+#define SCSMR_1 0xFFFE8800
+#define SCSMR_2 0xFFFE9000
+#define SCSMR_3 0xFFFE9800
+#define SCIF0_BASE SCSMR_0
+#define SCIF1_BASE SCSMR_1
+#define SCIF2_BASE SCSMR_2
+#define SCIF3_BASE SCSMR_3
+
+/* Timer(CMT) */
+#define CMSTR 0xFFFEC000
+#define CMCSR_0 0xFFFEC002
+#define CMCNT_0 0xFFFEC004
+#define CMCOR_0 0xFFFEC006
+#define CMCSR_1 0xFFFEC008
+#define CMCNT_1 0xFFFEC00A
+#define CMCOR_1 0xFFFEC00C
+
+/* PFC */
+#define PACRH3 0xFFFE380A
+#define PACRH2 0xFFFE380C
+#define PACRH1 0xFFFE380E
+#define PACRL4 0xFFFE3810
+#define PACRL3 0xFFFE3812
+#define PACRL2 0xFFFE3814
+#define PACRL1 0xFFFE3816
+#define PBCR3 0xFFFE3892
+#define PBCR2 0xFFFE3894
+#define PBCR1 0xFFFE3896
+#define PCCRL1 0xFFFE3916
+#define PDCRH4 0xFFFE3988
+#define PDCRH3 0xFFFE398A
+#define PDCRH2 0xFFFE398C
+#define PDCRH1 0xFFFE398E
+#define PDCRL4 0xFFFE3990
+#define PDCRL3 0xFFFE3992
+#define PECRH1 0xFFFE3A0E
+#define PECRL4 0xFFFE3A10
+#define PECRL3 0xFFFE3A12
+#define PECRL2 0xFFFE3A14
+#define IFCR 0xFFFE3A22
+
+/* On chip oscillator circuits */
+#define FRQCR 0xFFFE0010
+#define MCLKCR 0xFFFE0410
+/* Watchdog timer */
+#define WTCNT 0xFFFE0002
+#define WTCSR 0xFFFE0000
+
+#endif /* _ASM_CPU_SH7206_H_ */
--
1.8.5.3
^ permalink raw reply related [flat|nested] 8+ messages in thread* [U-Boot] [PATCH v2 4/6] SH2A cache support
2014-02-13 14:13 [U-Boot] [PATCH v2 0/6] Add target board MS7206SE Yoshinori Sato
` (2 preceding siblings ...)
2014-02-13 14:13 ` [U-Boot] [PATCH v2 3/6] Add SH7206 support Yoshinori Sato
@ 2014-02-13 14:13 ` Yoshinori Sato
2014-02-13 14:13 ` [U-Boot] [PATCH v2 5/6] Module enabler cleanup Yoshinori Sato
2014-02-13 14:13 ` [U-Boot] [PATCH v2 6/6] Various update Yoshinori Sato
5 siblings, 0 replies; 8+ messages in thread
From: Yoshinori Sato @ 2014-02-13 14:13 UTC (permalink / raw)
To: u-boot
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/cpu/sh2/Makefile | 6 ++
arch/sh/cpu/sh2/cache-sh2a.c | 145 ++++++++++++++++++++++++++++++++++++++++++
arch/sh/cpu/sh2/cpu.c | 31 ---------
arch/sh/cpu/sh2/nocache.c | 36 +++++++++++
arch/sh/include/asm/cpu_sh2.h | 10 ---
5 files changed, 187 insertions(+), 41 deletions(-)
create mode 100644 arch/sh/cpu/sh2/cache-sh2a.c
create mode 100644 arch/sh/cpu/sh2/nocache.c
diff --git a/arch/sh/cpu/sh2/Makefile b/arch/sh/cpu/sh2/Makefile
index a19ed5e..6a11448 100644
--- a/arch/sh/cpu/sh2/Makefile
+++ b/arch/sh/cpu/sh2/Makefile
@@ -4,9 +4,15 @@
#
# Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
# Copyright (C) 2008 Renesas Solutions Corp.
+# Copyright (C) 2013 Yoshinori Sato <ysato@users.sourceforge.jp>
#
# SPDX-License-Identifier: GPL-2.0+
#
extra-y = start.o
obj-y = cpu.o interrupts.o watchdog.o
+ifdef CONFIG_SH2A
+obj-y += cache-sh2a.o
+else
+obj-y += nocache.o
+endif
diff --git a/arch/sh/cpu/sh2/cache-sh2a.c b/arch/sh/cpu/sh2/cache-sh2a.c
new file mode 100644
index 0000000..ae59797
--- /dev/null
+++ b/arch/sh/cpu/sh2/cache-sh2a.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) 2013 Yoshinori Sato <ysato@users.sourceforge.jp>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+/*
+ * Jump to cache disabled area
+ * When handling caches, we need to do it from non-cache area.
+ */
+#define jump_to_uncacheable() \
+do { \
+ unsigned long __dummy; \
+ __asm__ __volatile__( \
+ "mov.l 1f, %0\n\t" \
+ "or %1, %0\n\t" \
+ "jmp @%0\n\t" \
+ " nop\n\t" \
+ ".balign 4\n" \
+ "1: .long 2f\n" \
+ "2:" \
+ : "=&r" (__dummy) \
+ : "r" (0x20000000)); \
+} while (0)
+
+/*
+ * Back to cache area.
+ */
+#define back_to_cacheable() \
+do { \
+ unsigned long __dummy; \
+ __asm__ __volatile__( \
+ "nop;nop;nop;nop;nop;nop;nop\n\t" \
+ "mov.l 1f, %0\n\t" \
+ "jmp @%0\n\t" \
+ " nop\n\t" \
+ ".balign 4\n" \
+ "1: .long 2f\n" \
+ "2:" \
+ : "=&r" (__dummy)); \
+} while (0)
+
+#define CACHE_OC_NUM_ENTRIES 128
+#define CACHE_OC_NUM_WAYS 4
+#define CACHE_OC_ADDRESS_ARRAY 0xf0800000
+#define CACHE_OC_WAY_SHIFT 11
+#define CACHE_OC_ENTRY_SHIFT 2
+#define CACHE_UPDATED 0x02
+
+static inline void cache_wback_all(void)
+{
+ unsigned long addr, data, i, j;
+
+ for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) {
+ for (j = 0; j < CACHE_OC_NUM_WAYS; j++) {
+ addr = CACHE_OC_ADDRESS_ARRAY
+ | (j << CACHE_OC_WAY_SHIFT)
+ | (i << CACHE_OC_ENTRY_SHIFT);
+ data = inl(addr);
+ if (data & CACHE_UPDATED) {
+ data &= ~CACHE_UPDATED;
+ outl(data, addr);
+ }
+ }
+ }
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+ unsigned long entry;
+ unsigned long tag;
+ size = (size + 3) & ~3;
+ jump_to_uncacheable();
+ while (size > 0) {
+ entry = addr & 0x000003ff0;
+ tag = addr & 0x1ffff0000;
+ /* I-Cache flush */
+ outl(tag, 0xf0000008 | entry);
+ /* D-Cache flush with wb */
+ outl(tag, 0xf0800008 | entry);
+ addr += 4;
+ size -= 4;
+ }
+ back_to_cacheable();
+}
+
+void icache_enable(void)
+{
+ unsigned long ccr;
+ ccr = readl(CCR1);
+ ccr |= 0x00000900;
+ jump_to_uncacheable();
+ writel(ccr, CCR1);
+ back_to_cacheable();
+}
+
+void icache_disable(void)
+{
+ unsigned long ccr;
+ ccr = readl(CCR1);
+ ccr &= ~0x00000100;
+ jump_to_uncacheable();
+ writel(ccr, CCR1);
+ back_to_cacheable();
+}
+
+int icache_status(void)
+{
+ unsigned long ccr;
+ ccr = readl(CCR1);
+ return ((ccr & 0x00000100) != 0);
+}
+
+void dcache_enable(void)
+{
+ unsigned long ccr;
+ ccr = readl(CCR1);
+ ccr |= 0x00000009;
+ jump_to_uncacheable();
+ writel(ccr, CCR1);
+ back_to_cacheable();
+}
+
+void dcache_disable(void)
+{
+ unsigned long ccr;
+ ccr = readl(CCR1);
+ ccr &= ~0x00000001;
+ jump_to_uncacheable();
+ cache_wback_all();
+ writel(ccr, CCR1);
+ back_to_cacheable();
+}
+
+int dcache_status(void)
+{
+ unsigned long ccr;
+ ccr = readl(CCR1);
+ return ((ccr & 0x00000001) != 0);
+}
diff --git a/arch/sh/cpu/sh2/cpu.c b/arch/sh/cpu/sh2/cpu.c
index a2f856f..b401d08 100644
--- a/arch/sh/cpu/sh2/cpu.c
+++ b/arch/sh/cpu/sh2/cpu.c
@@ -52,34 +52,3 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
reset_cpu(0);
return 0;
}
-
-void flush_cache(unsigned long addr, unsigned long size)
-{
-
-}
-
-void icache_enable(void)
-{
-}
-
-void icache_disable(void)
-{
-}
-
-int icache_status(void)
-{
- return 0;
-}
-
-void dcache_enable(void)
-{
-}
-
-void dcache_disable(void)
-{
-}
-
-int dcache_status(void)
-{
- return 0;
-}
diff --git a/arch/sh/cpu/sh2/nocache.c b/arch/sh/cpu/sh2/nocache.c
new file mode 100644
index 0000000..29a8858
--- /dev/null
+++ b/arch/sh/cpu/sh2/nocache.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2013 Yoshinori Sato <ysato@users.sourceforge.jp>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* dummy cache control functions */
+void flush_cache(unsigned long addr, unsigned long size)
+{
+}
+
+void icache_enable(void)
+{
+}
+
+void icache_disable(void)
+{
+}
+
+int icache_status(void)
+{
+ return 0;
+}
+
+void dcache_enable(void)
+{
+}
+
+void dcache_disable(void)
+{
+}
+
+int dcache_status(void)
+{
+ return 0;
+}
diff --git a/arch/sh/include/asm/cpu_sh2.h b/arch/sh/include/asm/cpu_sh2.h
index ca7b630..b84dad4 100644
--- a/arch/sh/include/asm/cpu_sh2.h
+++ b/arch/sh/include/asm/cpu_sh2.h
@@ -8,16 +8,6 @@
#ifndef _ASM_CPU_SH2_H_
#define _ASM_CPU_SH2_H_
-/* cache control */
-#define CCR_CACHE_STOP 0x00000008
-#define CCR_CACHE_ENABLE 0x00000005
-#define CCR_CACHE_ICI 0x00000008
-
-#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
-#define CACHE_OC_WAY_SHIFT 13
-#define CACHE_OC_NUM_ENTRIES 256
-#define CACHE_OC_ENTRY_SHIFT 4
-
#if defined(CONFIG_CPU_SH7203)
# include <asm/cpu_sh7203.h>
#elif defined(CONFIG_CPU_SH7206)
--
1.8.5.3
^ permalink raw reply related [flat|nested] 8+ messages in thread* [U-Boot] [PATCH v2 5/6] Module enabler cleanup
2014-02-13 14:13 [U-Boot] [PATCH v2 0/6] Add target board MS7206SE Yoshinori Sato
` (3 preceding siblings ...)
2014-02-13 14:13 ` [U-Boot] [PATCH v2 4/6] SH2A cache support Yoshinori Sato
@ 2014-02-13 14:13 ` Yoshinori Sato
2014-02-13 14:13 ` [U-Boot] [PATCH v2 6/6] Various update Yoshinori Sato
5 siblings, 0 replies; 8+ messages in thread
From: Yoshinori Sato @ 2014-02-13 14:13 UTC (permalink / raw)
To: u-boot
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/cpu/sh2/cpu.c | 27 ++++++++++++---------------
arch/sh/include/asm/cpu_sh2.h | 3 +++
arch/sh/include/asm/cpu_sh2a.h | 16 ++++++++++++++++
3 files changed, 31 insertions(+), 15 deletions(-)
create mode 100644 arch/sh/include/asm/cpu_sh2a.h
diff --git a/arch/sh/cpu/sh2/cpu.c b/arch/sh/cpu/sh2/cpu.c
index b401d08..0a6a58b 100644
--- a/arch/sh/cpu/sh2/cpu.c
+++ b/arch/sh/cpu/sh2/cpu.c
@@ -10,16 +10,17 @@
#include <asm/processor.h>
#include <asm/io.h>
-#define STBCR4 0xFFFE040C
-#define cmt_clock_enable() do {\
- writeb(readb(STBCR4) & ~0x04, STBCR4);\
- } while (0)
-#define scif0_enable() do {\
- writeb(readb(STBCR4) & ~0x80, STBCR4);\
- } while (0)
-#define scif3_enable() do {\
- writeb(readb(STBCR4) & ~0x10, STBCR4);\
- } while (0)
+#if defined(CONFIG_CONS_SCIF0)
+# define CH 0
+#elif defined(CONFIG_CONS_SCIF1)
+# define CH 1
+#elif defined(CONFIG_CONS_SCIF2)
+# define CH 2
+#elif defined(CONFIG_CONS_SCIF3)
+# define CH 3
+#else
+# error "Default SCIF doesn't set....."
+#endif
int checkcpu(void)
{
@@ -30,11 +31,7 @@ int checkcpu(void)
int cpu_init(void)
{
/* SCIF enable */
-#if defined(CONFIG_CONS_SCIF3)
- scif3_enable();
-#else
- scif0_enable();
-#endif
+ scif_enable(CH);
/* CMT clock enable */
cmt_clock_enable() ;
return 0;
diff --git a/arch/sh/include/asm/cpu_sh2.h b/arch/sh/include/asm/cpu_sh2.h
index b84dad4..deadece 100644
--- a/arch/sh/include/asm/cpu_sh2.h
+++ b/arch/sh/include/asm/cpu_sh2.h
@@ -8,6 +8,9 @@
#ifndef _ASM_CPU_SH2_H_
#define _ASM_CPU_SH2_H_
+#if defined(CONFIG_SH2A)
+# include <asm/cpu_sh2a.h>
+#endif
#if defined(CONFIG_CPU_SH7203)
# include <asm/cpu_sh7203.h>
#elif defined(CONFIG_CPU_SH7206)
diff --git a/arch/sh/include/asm/cpu_sh2a.h b/arch/sh/include/asm/cpu_sh2a.h
new file mode 100644
index 0000000..7262a2a
--- /dev/null
+++ b/arch/sh/include/asm/cpu_sh2a.h
@@ -0,0 +1,16 @@
+#ifndef _ASM_CPU_SH2A_H_
+#define _ASM_CPU_SH2A_H_
+
+/* module enable */
+#define STBCR4 0xFFFE040C
+#define scif_enable(ch) \
+do { \
+ if (ch < 4) { \
+ unsigned char mask = 1 << (7 - ch); \
+ writeb((readb(STBCR4) & ~mask), STBCR4);\
+ } \
+} while (0)
+
+#define cmt_clock_enable() \
+ writeb((readb(STBCR4) & ~0x04), STBCR4)
+#endif
--
1.8.5.3
^ permalink raw reply related [flat|nested] 8+ messages in thread* [U-Boot] [PATCH v2 6/6] Various update
2014-02-13 14:13 [U-Boot] [PATCH v2 0/6] Add target board MS7206SE Yoshinori Sato
` (4 preceding siblings ...)
2014-02-13 14:13 ` [U-Boot] [PATCH v2 5/6] Module enabler cleanup Yoshinori Sato
@ 2014-02-13 14:13 ` Yoshinori Sato
5 siblings, 0 replies; 8+ messages in thread
From: Yoshinori Sato @ 2014-02-13 14:13 UTC (permalink / raw)
To: u-boot
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/config.mk | 3 +++
arch/sh/cpu/sh2/config.mk | 4 +++-
arch/sh/cpu/sh2/start.S | 2 +-
3 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/sh/config.mk b/arch/sh/config.mk
index 758c070..abd419a 100644
--- a/arch/sh/config.mk
+++ b/arch/sh/config.mk
@@ -11,6 +11,9 @@ CONFIG_STANDALONE_LOAD_ADDR ?= 0x8C000000
ifeq ($(CPU),sh2)
CONFIG_STANDALONE_LOAD_ADDR += -EB
endif
+ifeq ($(CPU),sh2a)
+CONFIG_STANDALONE_LOAD_ADDR += -m2a-nofpu
+endif
PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__
PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(CONFIG_SYS_TEXT_BASE)
diff --git a/arch/sh/cpu/sh2/config.mk b/arch/sh/cpu/sh2/config.mk
index 69273b4..a012162 100644
--- a/arch/sh/cpu/sh2/config.mk
+++ b/arch/sh/cpu/sh2/config.mk
@@ -8,7 +8,7 @@
ENDIANNESS += -EB
ifdef CONFIG_SH2A
-PLATFORM_CPPFLAGS += -m2a -m2a-nofpu -mb -ffreestanding
+PLATFORM_CPPFLAGS += -m2a-nofpu -mb -ffreestanding
else # SH2
PLATFORM_CPPFLAGS += -m3e -mb
endif
@@ -16,3 +16,5 @@ PLATFORM_CPPFLAGS += -DCONFIG_SH2 $(call cc-option,-mno-fdpic)
PLATFORM_RELFLAGS += -ffixed-r13
PLATFORM_LDFLAGS += $(ENDIANNESS)
+
+USE_PRIVATE_LIBGCC = yes
diff --git a/arch/sh/cpu/sh2/start.S b/arch/sh/cpu/sh2/start.S
index 5b92a01..efda8e2 100644
--- a/arch/sh/cpu/sh2/start.S
+++ b/arch/sh/cpu/sh2/start.S
@@ -14,7 +14,7 @@
.global _start
_sh_start:
- .long 0x00000010 /* Ppower ON reset PC*/
+ .long 0x00000010 /* Power ON reset PC*/
.long 0x00000000
.long 0x00000010 /* Manual reset PC */
.long 0x00000000
--
1.8.5.3
^ permalink raw reply related [flat|nested] 8+ messages in thread