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From: Chin Liang See <clsee@altera.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v4 1/2] watchdog/denali: Adding DesignWare watchdog driver support
Date: Tue, 4 Mar 2014 17:45:31 -0600	[thread overview]
Message-ID: <1393976731.2356.0.camel@clsee-VirtualBox.altera.com> (raw)
In-Reply-To: <53106555.1070405@monstr.eu>

On Fri, 2014-02-28 at 11:30 +0100, Michal Simek wrote:
> On 02/27/2014 08:53 PM, Chin Liang See wrote:
> > To add the DesignWare watchdog driver support. It required
> > information such as register base address and clock info from
> > configuration header file  within include/configs folder.
> > 
> > Signed-off-by: Chin Liang See <clsee@altera.com>
> > Cc: Anatolij Gustschin <agust@denx.de>
> > Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> > Cc: Heiko Schocher <hs@denx.de>
> > Cc: Tom Rini <trini@ti.com>
> > ---
> > Changes for v4
> > - Add 2014 to license header
> > Changes for v3
> > - Split to 2 series patch
> > Changes for v2
> > - Enable this driver at socfpga_cyclone5 board
> > ---
> >  drivers/watchdog/Makefile         |    1 +
> >  drivers/watchdog/designware_wdt.c |   73 +++++++++++++++++++++++++++++++++++++
> >  2 files changed, 74 insertions(+)
> >  create mode 100644 drivers/watchdog/designware_wdt.c
> > 
> > diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
> > index 06ced10..0276a10 100644
> > --- a/drivers/watchdog/Makefile
> > +++ b/drivers/watchdog/Makefile
> > @@ -15,3 +15,4 @@ obj-$(CONFIG_S5P)               += s5p_wdt.o
> >  obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
> >  obj-$(CONFIG_BFIN_WATCHDOG)  += bfin_wdt.o
> >  obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
> > +obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
> > diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c
> > new file mode 100644
> > index 0000000..6abee81
> > --- /dev/null
> > +++ b/drivers/watchdog/designware_wdt.c
> > @@ -0,0 +1,73 @@
> > +/*
> > + * Copyright (C) 2013-2014 Altera Corporation <www.altera.com>
> > + *
> > + * SPDX-License-Identifier:	GPL-2.0+
> > + */
> > +
> > +#include <common.h>
> > +#include <watchdog.h>
> > +#include <asm/io.h>
> > +#include <asm/utils.h>
> > +
> > +#define DW_WDT_CR	0x00
> > +#define DW_WDT_TORR	0x04
> > +#define DW_WDT_CRR	0x0C
> > +
> > +#define DW_WDT_CR_EN_OFFSET	0x00
> > +#define DW_WDT_CR_RMOD_OFFSET	0x01
> > +#define DW_WDT_CR_RMOD_VAL	0x00
> > +#define DW_WDT_CRR_RESTART_VAL	0x76
> > +
> > +/*
> > + * Set the watchdog time interval.
> > + * Counter is 32 bit.
> > + */
> > +int designware_wdt_settimeout(unsigned int timeout)
> > +{
> > +	signed int i;
> > +	/* calculate the timeout range value */
> > +	i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ)) - 16;
> > +	if (i > 15)
> > +		i = 15;
> > +	if (i < 0)
> > +		i = 0;
> > +
> > +	writel((i | (i<<4)), (CONFIG_DW_WDT_BASE + DW_WDT_TORR));
> 
> i << 4

Fixed

> 
> 
> > +	return 0;
> > +}
> > +
> > +void designware_wdt_enable(void)
> > +{
> > +	writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) |
> > +	       (0x1 << DW_WDT_CR_EN_OFFSET)),
> > +	       (CONFIG_DW_WDT_BASE + DW_WDT_CR));
> > +}
> > +
> > +unsigned int designware_wdt_is_enabled(void)
> > +{
> > +	unsigned long val;
> > +	val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR));
> > +	return val & 0x1;
> > +}
> 
> all 3 functions above I believe should be static because
> you use them just here.

Yup, I can enhance that.
Thanks

Chin Liang


> 
> Thanks,
> Michal
> 

  reply	other threads:[~2014-03-04 23:45 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-02-27 19:53 [U-Boot] [PATCH v4 1/2] watchdog/denali: Adding DesignWare watchdog driver support Chin Liang See
2014-02-28 10:30 ` Michal Simek
2014-03-04 23:45   ` Chin Liang See [this message]
  -- strict thread matches above, loose matches on Subject: below --
2014-03-05  2:51 Chin Liang See
2014-04-07 16:27 ` Albert ARIBAUD

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