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From: Lucas Stach <dev@lynxeye.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] ARM: tegra: use a CPU freq that all SKUs can support
Date: Wed, 07 May 2014 21:57:16 +0200	[thread overview]
Message-ID: <1399492636.2266.4.camel@tellur> (raw)
In-Reply-To: <1398367830-6814-1-git-send-email-swarren@wwwdotorg.org>

Hi Stephen,

I was just porting this change to barebox and stumbled upon a few errors
here.

Am Donnerstag, den 24.04.2014, 13:30 -0600 schrieb Stephen Warren:
> From: Stephen Warren <swarren@nvidia.com>
> 
[...]
> diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c
> index 85a945bc7918..0f52e54239e1 100644
> --- a/arch/arm/cpu/arm720t/tegra30/cpu.c
> +++ b/arch/arm/cpu/arm720t/tegra30/cpu.c
> @@ -41,10 +41,18 @@ void tegra_i2c_ll_write_data(uint data, uint config)
>  	writel(config, &reg->cnfg);
>  }
>  
> +#define TPS62366A_I2C_ADDR		0x60

The I2C address for this chip on Beaver is 0xc0, not 0x60. I don't know
about Cardhu.

> +#define TPS62366A_SET1_REG		0x01
> +#define TPS62366A_SET1_DATA		(0x46 | TPS62366A_SET1_REG)

This should be (0x4600 | TPS62366A_SET1_REG).

> +
> +#define TPS62361B_I2C_ADDR		0x60
> +#define TPS62361B_SET3_REG		0x03
> +#define TPS62361B_SET3_DATA		(0x46 | TPS62361B_SET3_REG)
Same here.

Only with those fixed I can verify vdd_core to ramp up to 1,2V on
Beaver. Without the changes vdd_core stays at the default 1,16V.

Regards,
Lucas

  reply	other threads:[~2014-05-07 19:57 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-04-24 19:30 [U-Boot] [PATCH] ARM: tegra: use a CPU freq that all SKUs can support Stephen Warren
2014-05-07 19:57 ` Lucas Stach [this message]
2014-05-07 20:13   ` Stephen Warren

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