From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chin Liang See Date: Fri, 16 May 2014 03:42:45 -0500 Subject: [U-Boot] Mainline u-boot SPL for socfpga In-Reply-To: <201405150701.25786.manningc2@actrix.gen.nz> References: <20140514164258.GA10393@amd.pavel.ucw.cz> <201405150701.25786.manningc2@actrix.gen.nz> Message-ID: <1400229765.2030.4.camel@clsee-VirtualBox.altera.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi, On Thu, 2014-05-15 at 07:01 +1200, Charles Manning wrote: > On Thursday 15 May 2014 04:42:58 Pavel Machek wrote: > > Hi! > > > > > I am trying to understand the state of the socfpga preloader in mainline > > > u-boot. > > > > > > >From what I see, this is broken and perhaps has never worked. > > > > That's correct AFAICT. Yup, Preloader without the SDRAM would not work correctly. > > > > > When I build the code in u-boot-socfpga I get a healthy working > > > u-boot-spl.bin of approx 45kbytes. > > > > > > When I build the mainline u-boot code I get a broken u-boot-spl.bin of > > > approx 3kbytes. > > > > > > It seems the mainline u-boot is missing stuff, including the all-critical > > > sdram initialisation without which the SPL is useless. > > > > Are you able to build working u-boot proper from recent sources? > > > > I know u-boot SPL misses critical parts, but I was told that u-boot > > proper should have everything. Only... I was not able to get it to > > work. [I'm attempting to load recent u-boot from patched/old u-boot; I > > know this is not exactly recommended, but due to spl/proper split, it > > should work AFAIK... and does for old versions.] > > I have not tried booting u-boot proper from mainline. It just seemed pointless > to me to be working from 2 source trees to make a single product. > > I will give it a go though. Actually the U-Boot is working. You just need to #undef CONFIG_SOCFPGA_VIRTUAL_TARGET and build it. I loaded it using a working Preloader and I can reach the U-Boot console. U-Boot SPL 2013.01.01 (May 16 2014 - 10:42:39) BOARD : Altera SOCFPGA Cyclone V Board CLOCK: EOSC1 clock 25000 KHz CLOCK: EOSC2 clock 25000 KHz CLOCK: F2S_SDR_REF clock 0 KHz CLOCK: F2S_PER_REF clock 0 KHz CLOCK: MPU clock 925 MHz CLOCK: DDR clock 400 MHz CLOCK: UART clock 100000 KHz CLOCK: MMC clock 50000 KHz CLOCK: QSPI clock 370000 KHz INFO : Watchdog enabled SDRAM: Initializing MMR registers SDRAM: Calibrating PHY SEQ.C: Preparing to start memory calibration SEQ.C: CALIBRATION PASSED SDRAM: 1024 MiB SDRAM: ECC Enabled ALTERA DWMMC: 0 reading u-boot.img reading u-boot.img U-Boot 2014.07-rc1-00079-g2072e72-dirty (May 16 2014 - 15:54:55) CPU : Altera SOCFPGA Platform BOARD : Altera SOCFPGA Cyclone5 Board DRAM: 1 GiB WARNING: Caches not enabled Using default environment In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 Wrong Image Format for bootm command ERROR: can't get kernel image! SOCFPGA_CYCLONE5 # help ? - alias for 'help' base - print or set address offset bdinfo - print Board Info structure boot - boot default, i.e., run 'bootcmd' bootd - boot default, i.e., run 'bootcmd' bootm - boot application image from memory bootp - boot image via network using BOOTP/TFTP protocol cmp - memory compare coninfo - print console devices and information cp - memory copy crc32 - checksum calculation echo - echo args to console editenv - edit environment variable env - environment handling commands exit - exit script false - do nothing, unsuccessfully fatinfo - print information about filesystem fatload - load binary file from a dos filesystem fatls - list files in a directory (default /) fdt - flattened device tree utility commands go - start application at address 'addr' help - print command description/usage iminfo - print header information for application image imxtract- extract a part of a multi-image itest - return true/false on integer compare loadb - load binary file over serial line (kermit mode) loads - load S-Record file over serial line loadx - load binary file over serial line (xmodem mode) loady - load binary file over serial line (ymodem mode) loop - infinite loop on address range md - memory display mm - memory modify (auto-incrementing address) mw - memory write (fill) nfs - boot image via network using NFS protocol nm - memory modify (constant address) printenv- print environment variables reset - Perform RESET of the CPU run - run commands in an environment variable setenv - set environment variables showvar - print local hushshell variables sleep - delay execution for some time source - run script from memory test - minimal test like /bin/sh tftpboot- boot image via network using TFTP protocol true - do nothing, successfully version - print monitor, compiler and linker version SOCFPGA_CYCLONE5 # > > As Chin Liang See has said, there are two issues thwarting this: legal AND > source conformance. The code we can fix, the legal can only be fixed by > bending Altera - I am going to do that too. We are making some progress on this. Once we have final green light, we will start the upstreaming of SDRAM code. :) Thanks Chin Liang > > Regards > > Charles