[U-Boot] [PATCH 2/2] sunxi: Set the AUXCR L2EN bit for sun4i/sun5i in FEL boot mode

[Ian Campbell <ijc@hellion.org.uk>]

On Sat, 2014-07-19 at 13:20 +0200, Hans de Goede wrote:
> Hi,
> 
> On 07/18/2014 07:09 PM, Siarhei Siamashka wrote:
> > This is needed to have feature parity with the normal boot mode,
> > where the L2EN bit in the CP15 Auxiliary Control Register is set
> > by the BROM code right from the start.
> >
> > If this is not done, the Linux system ends up booted with the L2 cache
> > disabled.
> >
> > Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
> > ---
> >   arch/arm/cpu/armv7/sunxi/board.c | 12 ++++++++++++
> >   1 file changed, 12 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
> > index 49c9448..86cf4c9 100644
> > --- a/arch/arm/cpu/armv7/sunxi/board.c
> > +++ b/arch/arm/cpu/armv7/sunxi/board.c
> > @@ -69,6 +69,18 @@ void s_init(void)
> >   		"mcr p15, 0, r0, c1, c0, 1\n");
> >   #endif
> >
> > +#if defined(CONFIG_SPL_FEL) && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I))
> > +	/* For ARM Cortex-A8 based hardware (sun4i and sun5i), the L2EN bit is
> > +	 * set by the BROM code in the "normal" mode, but not in the "FEL" mode.
> > +	 * Here we fix this inconsistency in the Auxiliary Ctl reg by also
> > +	 * setting the missing L2EN bit.
> > +	 */
> > +	asm volatile(
> > +		"mrc p15, 0, r0, c1, c0, 1\n"
> > +		"orr r0, r0, #2\n"
> > +		"mcr p15, 0, r0, c1, c0, 1\n" : : : "r0");
> > +#endif
> > +
> 
> Wouldn't it be better to do this in the start_fel.S file you've introduced in
> the first patch of this series ?

That wouldn't remove the need for the ifdef if that's what you are
thinking since it still needs to be sun4i/sun5i specific.

I think doing it here is in keeping with setting ACTLR.SMP on the
sun6i/sun7i platforms which is just above the context here.

Acked-by: Ian Campbell <ijc@hellion.org.uk>

Although I also wouldn't object to doing it in in start_fel.S if that is
preferred.

I expect this needs to be done on secondary processors. Need to keep
that in mind if/when someone works on PSCI for sun[45]i.

Ian.