From: Ian Campbell <ijc@hellion.org.uk>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 03/14] sunxi: dram: Respect the DDR3 reset timing requirements
Date: Mon, 21 Jul 2014 19:46:25 +0100 [thread overview]
Message-ID: <1405968385.27009.65.camel@dagon.hellion.org.uk> (raw)
In-Reply-To: <1405700585-13546-4-git-send-email-siarhei.siamashka@gmail.com>
On Fri, 2014-07-18 at 19:22 +0300, Siarhei Siamashka wrote:
> The RESET pin needs to be kept low for at least 200 us according
> to the DDR3 spec. So just do it the right way.
>
> This issue did not cause any visible major problems earlier, because
> the DRAM RESET pin is usually already low after the board reset. And
> the time gap before reaching the sunxi u-boot DRAM initialization
> code appeared to be sufficient.
>
> Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
next prev parent reply other threads:[~2014-07-21 18:46 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-18 16:22 [U-Boot] [PATCH 00/14] sunxi: Allwinner A10/A13/A20 DRAM controller fixes Siarhei Siamashka
2014-07-18 16:22 ` [U-Boot] [PATCH 01/14] sunxi: dram: Remove useless 'dramc_scan_dll_para()' function Siarhei Siamashka
2014-07-21 18:42 ` Ian Campbell
2014-07-18 16:22 ` [U-Boot] [PATCH 02/14] sunxi: dram: Remove broken super-standby remnants Siarhei Siamashka
2014-07-21 18:45 ` Ian Campbell
2014-07-18 16:22 ` [U-Boot] [PATCH 03/14] sunxi: dram: Respect the DDR3 reset timing requirements Siarhei Siamashka
2014-07-21 18:46 ` Ian Campbell [this message]
2014-07-18 16:22 ` [U-Boot] [PATCH 04/14] sunxi: dram: Code cleanup and comments for the CKE delay handling Siarhei Siamashka
2014-07-21 18:51 ` Ian Campbell
2014-07-25 1:41 ` Siarhei Siamashka
2014-07-25 7:27 ` Ian Campbell
2014-07-18 16:22 ` [U-Boot] [PATCH 05/14] sunxi: dram: Code cleanup for the impedance calibration Siarhei Siamashka
2014-07-21 19:20 ` Ian Campbell
2014-07-25 3:44 ` [U-Boot] [linux-sunxi] " Siarhei Siamashka
2014-07-25 7:30 ` Ian Campbell
2014-07-18 16:22 ` [U-Boot] [PATCH 06/14] sunxi: dram: Configurable MBUS clock speed (use PLL5 or PLL6) Siarhei Siamashka
2014-07-21 19:31 ` Ian Campbell
2014-07-25 4:00 ` Siarhei Siamashka
2014-07-25 7:31 ` Ian Campbell
2014-07-18 16:22 ` [U-Boot] [PATCH 07/14] sunxi: dram: Use divisor P=1 for PLL5 Siarhei Siamashka
2014-07-21 19:35 ` Ian Campbell
2014-07-18 16:22 ` [U-Boot] [PATCH 08/14] sunxi: dram: Improve DQS gate data training error handling Siarhei Siamashka
2014-07-21 19:36 ` Ian Campbell
2014-07-18 16:23 ` [U-Boot] [PATCH 09/14] sunxi: dram: Add a helper function 'mctl_get_number_of_lanes' Siarhei Siamashka
2014-07-21 19:41 ` Ian Campbell
2014-07-25 4:26 ` Siarhei Siamashka
2014-07-25 7:33 ` Ian Campbell
2014-07-18 16:23 ` [U-Boot] [PATCH 10/14] sunxi: dram: Configurable DQS gating window mode and delay Siarhei Siamashka
2014-07-18 16:23 ` [U-Boot] [PATCH 11/14] sunxi: dram: Support sun4i (Allwinner A10) and sun5i (Allwinner A13) Siarhei Siamashka
2014-07-21 19:49 ` Ian Campbell
2014-07-18 16:23 ` [U-Boot] [PATCH 12/14] sunxi: dram: Drop DDR2 support and assume only single rank DDR3 memory Siarhei Siamashka
2014-07-21 19:51 ` Ian Campbell
2014-07-25 4:36 ` Siarhei Siamashka
2014-07-18 16:23 ` [U-Boot] [PATCH 13/14] sunxi: dram: Derive write recovery delay from DRAM clock speed Siarhei Siamashka
2014-07-21 19:52 ` Ian Campbell
2014-07-18 16:23 ` [U-Boot] [PATCH 14/14] sunxi: dram: Autodetect DDR3 bus width and density Siarhei Siamashka
2014-07-21 19:54 ` Ian Campbell
2014-07-19 10:59 ` [U-Boot] [PATCH 00/14] sunxi: Allwinner A10/A13/A20 DRAM controller fixes Hans de Goede
2014-07-21 19:58 ` Ian Campbell
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