From: Ian Campbell <ijc@hellion.org.uk>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 05/14] sunxi: dram: Code cleanup for the impedance calibration
Date: Mon, 21 Jul 2014 20:20:20 +0100 [thread overview]
Message-ID: <1405970420.4100.11.camel@hastur.hellion.org.uk> (raw)
In-Reply-To: <1405700585-13546-6-git-send-email-siarhei.siamashka@gmail.com>
On Fri, 2014-07-18 at 19:22 +0300, Siarhei Siamashka wrote:
> Moved the impedance setup code part into a separate function. Added explicit
> wait for ZQ calibration completion before proceeding to the next initialization
> steps. Removed the CONFIG_SUN7I ifdef guard around the code, which has identical
> behaviour on sun4i/sun5i/sun7i. And if 'odt_en' is set in the 'dram_para' struct,
> then ODT now actually gets enabled in the DRAM_IOCR register (which the older
> code failed to do and was always running without ODT no matter the settings).
There's a few aspects of this code which don't seem to be explained
here.
Firstly if odt_en is not enabled we now skip setting the impedance.
Which seems logical but should me mentioned. It's also worth noting that
none of the platforms in u-boot-sunxi.git#master set odt_en
Secondly the weird sun7i magic has changed from
- setbits_le32(&dram->zqcr1, (0x1 << 24) | (0x1 << 1));
- if (para->tpr4 & 0x2)
- clrsetbits_le32(&dram->zqcr1, (0x1 << 24), (0x1 << 1));
into just a write of the raw value. This should be mentioned. Also this
now occurs after the call to dramc_clock_output_en().
Thirdly why do we not wait for ZQ calibration on sun7i?
Lastly it now seems to support calibration using an external resistor.
And neither half of that new if (zdata) seems to correspond to the old
code.
I think part of the problem here is that this patch is trying to do too
much in one go. If separating things out isn't possible (e.g. because
these changes are all interdependent) then it is important that the
commit message describes them. I'd also steer clear of describing this
as a code cleanup when it also has functional changes.
> + * Wait up to 1s for mask to be set in given reg.
> + */
> +static void await_bits_set(u32 *reg, u32 mask)
This could be combined with the existing await_completion into a
function which takes a mask and a val. Perhaps with convenience wrappers
for the two cases.
Ian.
next prev parent reply other threads:[~2014-07-21 19:20 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-18 16:22 [U-Boot] [PATCH 00/14] sunxi: Allwinner A10/A13/A20 DRAM controller fixes Siarhei Siamashka
2014-07-18 16:22 ` [U-Boot] [PATCH 01/14] sunxi: dram: Remove useless 'dramc_scan_dll_para()' function Siarhei Siamashka
2014-07-21 18:42 ` Ian Campbell
2014-07-18 16:22 ` [U-Boot] [PATCH 02/14] sunxi: dram: Remove broken super-standby remnants Siarhei Siamashka
2014-07-21 18:45 ` Ian Campbell
2014-07-18 16:22 ` [U-Boot] [PATCH 03/14] sunxi: dram: Respect the DDR3 reset timing requirements Siarhei Siamashka
2014-07-21 18:46 ` Ian Campbell
2014-07-18 16:22 ` [U-Boot] [PATCH 04/14] sunxi: dram: Code cleanup and comments for the CKE delay handling Siarhei Siamashka
2014-07-21 18:51 ` Ian Campbell
2014-07-25 1:41 ` Siarhei Siamashka
2014-07-25 7:27 ` Ian Campbell
2014-07-18 16:22 ` [U-Boot] [PATCH 05/14] sunxi: dram: Code cleanup for the impedance calibration Siarhei Siamashka
2014-07-21 19:20 ` Ian Campbell [this message]
2014-07-25 3:44 ` [U-Boot] [linux-sunxi] " Siarhei Siamashka
2014-07-25 7:30 ` Ian Campbell
2014-07-18 16:22 ` [U-Boot] [PATCH 06/14] sunxi: dram: Configurable MBUS clock speed (use PLL5 or PLL6) Siarhei Siamashka
2014-07-21 19:31 ` Ian Campbell
2014-07-25 4:00 ` Siarhei Siamashka
2014-07-25 7:31 ` Ian Campbell
2014-07-18 16:22 ` [U-Boot] [PATCH 07/14] sunxi: dram: Use divisor P=1 for PLL5 Siarhei Siamashka
2014-07-21 19:35 ` Ian Campbell
2014-07-18 16:22 ` [U-Boot] [PATCH 08/14] sunxi: dram: Improve DQS gate data training error handling Siarhei Siamashka
2014-07-21 19:36 ` Ian Campbell
2014-07-18 16:23 ` [U-Boot] [PATCH 09/14] sunxi: dram: Add a helper function 'mctl_get_number_of_lanes' Siarhei Siamashka
2014-07-21 19:41 ` Ian Campbell
2014-07-25 4:26 ` Siarhei Siamashka
2014-07-25 7:33 ` Ian Campbell
2014-07-18 16:23 ` [U-Boot] [PATCH 10/14] sunxi: dram: Configurable DQS gating window mode and delay Siarhei Siamashka
2014-07-18 16:23 ` [U-Boot] [PATCH 11/14] sunxi: dram: Support sun4i (Allwinner A10) and sun5i (Allwinner A13) Siarhei Siamashka
2014-07-21 19:49 ` Ian Campbell
2014-07-18 16:23 ` [U-Boot] [PATCH 12/14] sunxi: dram: Drop DDR2 support and assume only single rank DDR3 memory Siarhei Siamashka
2014-07-21 19:51 ` Ian Campbell
2014-07-25 4:36 ` Siarhei Siamashka
2014-07-18 16:23 ` [U-Boot] [PATCH 13/14] sunxi: dram: Derive write recovery delay from DRAM clock speed Siarhei Siamashka
2014-07-21 19:52 ` Ian Campbell
2014-07-18 16:23 ` [U-Boot] [PATCH 14/14] sunxi: dram: Autodetect DDR3 bus width and density Siarhei Siamashka
2014-07-21 19:54 ` Ian Campbell
2014-07-19 10:59 ` [U-Boot] [PATCH 00/14] sunxi: Allwinner A10/A13/A20 DRAM controller fixes Hans de Goede
2014-07-21 19:58 ` Ian Campbell
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