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From: Ian Campbell <ijc@hellion.org.uk>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 02/16] sunxi: dram: Remove broken super-standby remnants
Date: Tue, 05 Aug 2014 07:37:48 +0100	[thread overview]
Message-ID: <1407220668.23472.17.camel@dagon.hellion.org.uk> (raw)
In-Reply-To: <1407033174-24603-3-git-send-email-siarhei.siamashka@gmail.com>

On Sun, 2014-08-03 at 05:32 +0300, Siarhei Siamashka wrote:
> If the dram->ppwrsctl (SDR_DPCR) register has the lowest bit set to 1,
> this means that DRAM is currently in self-refresh mode and retaining the
> old data. Since we have no idea what to do in this situation yet, just
> set this register to 0 and initialize DRAM in the same way as on any
> normal reboot (discarding whatever was stored there).
> 
> This part of code was apparently used by the Allwinner boot0 bootloader
> to handle resume from the so-called super-standby mode. But this
> particular code got somehow mangled on the way from the boot0 bootloader
> to the u-boot-sunxi bootloader and has no chance of doing anything even
> remotely sane. For example:
> 1. in the original boot0 code we had "mctl_write_w(SDR_DPCR,
>    0x16510000)" (write to the register) and in the u-boot it now looks
>    like "setbits_le32(&dram->ppwrsctl, 0x16510000)" (set bits in the
>    register)
> 2. in the original boot0 code it was issuing three commands "0x12, 0x17,
>    0x13" (Self-Refresh entry, Self-Refresh exit, Refresh), but in the
>    u-boot they have become "0x12, 0x12, 0x13" (Self-Refresh entry,
>    Self-Refresh entry, Refresh)
> 
> Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>

Acked-by: Ian Campbell <ijc@hellion.org.uk>

  reply	other threads:[~2014-08-05  6:37 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-08-03  2:32 [U-Boot] [PATCH v2 00/16] sunxi: Allwinner A10/A13/A20 DRAM controller fixes Siarhei Siamashka
2014-08-03  2:32 ` [U-Boot] [PATCH v2 01/16] sunxi: dram: Remove useless 'dramc_scan_dll_para()' function Siarhei Siamashka
2014-08-03  2:32 ` [U-Boot] [PATCH v2 02/16] sunxi: dram: Remove broken super-standby remnants Siarhei Siamashka
2014-08-05  6:37   ` Ian Campbell [this message]
2014-08-03  2:32 ` [U-Boot] [PATCH v2 03/16] sunxi: dram: Respect the DDR3 reset timing requirements Siarhei Siamashka
2014-08-05  6:38   ` Ian Campbell
2014-08-03  2:32 ` [U-Boot] [PATCH v2 04/16] sunxi: dram: Fix CKE delay handling for sun4i/sun5i Siarhei Siamashka
2014-08-05  6:41   ` Ian Campbell
2014-08-03  2:32 ` [U-Boot] [PATCH v2 05/16] sunxi: dram: Remove broken impedance and ODT configuration code Siarhei Siamashka
2014-08-05  6:43   ` Ian Campbell
2014-08-03  2:32 ` [U-Boot] [PATCH v2 06/16] sunxi: dram: Do DDR3 reset in the same way on sun4i/sun5i/sun7i Siarhei Siamashka
2014-08-05  6:43   ` Ian Campbell
2014-08-03  2:32 ` [U-Boot] [PATCH v2 07/16] sunxi: dram: Add 'await_bits_clear'/'await_bits_set' helper functions Siarhei Siamashka
2014-08-05  6:44   ` Ian Campbell
2014-08-03  2:32 ` [U-Boot] [PATCH v2 08/16] sunxi: dram: Re-introduce the impedance calibration ond ODT Siarhei Siamashka
2014-08-05  6:47   ` Ian Campbell
2014-08-03  2:32 ` [U-Boot] [PATCH v2 09/16] sunxi: dram: Configurable MBUS clock speed (use PLL5 or PLL6) Siarhei Siamashka
2014-08-05  6:49   ` Ian Campbell
2014-08-03  2:32 ` [U-Boot] [PATCH v2 10/16] sunxi: dram: Use divisor P=1 for PLL5 Siarhei Siamashka
2014-08-03  2:32 ` [U-Boot] [PATCH v2 11/16] sunxi: dram: Improve DQS gate data training error handling Siarhei Siamashka
2014-08-03  2:32 ` [U-Boot] [PATCH v2 12/16] sunxi: dram: Add a helper function 'mctl_get_number_of_lanes' Siarhei Siamashka
2014-08-05  6:50   ` Ian Campbell
2014-08-03  2:32 ` [U-Boot] [PATCH v2 13/16] sunxi: dram: Configurable DQS gating window mode and delay Siarhei Siamashka
2014-08-05  6:53   ` Ian Campbell
2014-08-03  2:32 ` [U-Boot] [PATCH v2 14/16] sunxi: dram: Drop DDR2 support and assume only single rank DDR3 memory Siarhei Siamashka
2014-08-05  6:54   ` Ian Campbell
2014-08-03  2:32 ` [U-Boot] [PATCH v2 15/16] sunxi: dram: Derive write recovery delay from DRAM clock speed Siarhei Siamashka
2014-08-03  2:32 ` [U-Boot] [PATCH v2 16/16] sunxi: dram: Autodetect DDR3 bus width and density Siarhei Siamashka
2014-08-05  7:02 ` [U-Boot] [PATCH v2 00/16] sunxi: Allwinner A10/A13/A20 DRAM controller fixes Ian Campbell
2014-08-05 10:00   ` Hans de Goede

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