From: Tim Harvey <tharvey@gateworks.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] pci: mx6: fix occasional link failures
Date: Thu, 7 Aug 2014 22:57:29 -0700 [thread overview]
Message-ID: <1407477449-7447-1-git-send-email-tharvey@gateworks.com> (raw)
According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable
for SS function) must remain deasserted until the reference clock is running
at the appropriate frequency.
Without this patch we find a high link failure rate (>5%) on certain
IMX6 boards at various temperatures.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
drivers/pci/pcie_imx.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index c48737e..a3982c4 100644
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -509,10 +509,6 @@ static int imx6_pcie_deassert_core_reset(void)
imx6_pcie_toggle_power();
- /* Enable PCIe */
- clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
- setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
-
enable_pcie_clock();
/*
@@ -521,6 +517,10 @@ static int imx6_pcie_deassert_core_reset(void)
*/
mdelay(50);
+ /* Enable PCIe */
+ clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
+ setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
+
imx6_pcie_toggle_reset();
return 0;
--
1.8.3.2
next reply other threads:[~2014-08-08 5:57 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-08 5:57 Tim Harvey [this message]
2014-08-08 12:27 ` [U-Boot] [PATCH] pci: mx6: fix occasional link failures Marek Vasut
2014-08-08 13:02 ` Fabio Estevam
2014-08-08 13:33 ` Marek Vasut
2014-08-08 15:35 ` Fabio Estevam
2014-08-09 11:51 ` Marek Vasut
2014-08-09 15:37 ` Fabio Estevam
2014-08-09 19:11 ` Fabio Estevam
2014-08-10 20:41 ` Marek Vasut
2014-08-20 10:38 ` Stefano Babic
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