From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Tue, 19 Aug 2014 13:28:01 -0700 Subject: [U-Boot] [Patch v2 4/5] ARMv8/ls2085a: Enable secondary cores In-Reply-To: <1408480082-4617-1-git-send-email-yorksun@freescale.com> References: <1408480082-4617-1-git-send-email-yorksun@freescale.com> Message-ID: <1408480082-4617-4-git-send-email-yorksun@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Spin table is at the very beginning of boot code. Each core has an individual release address within the spin table, the ft_cpu_setup fn updates the "cpu-release-addr" property of each cpu node with the corresponding release address. Also fix CPU_RELEASE_ADDR to point to secondary_boot_func. Signed-off-by: York Sun Signed-off-by: Arnab Basu --- Change log v2: Use individual spin table for each core by default board/freescale/ls2085a/ls2085a.c | 2 ++ include/configs/ls2085a_common.h | 9 ++++++--- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c index a18db1d..3daa787 100644 --- a/board/freescale/ls2085a/ls2085a.c +++ b/board/freescale/ls2085a/ls2085a.c @@ -88,6 +88,8 @@ void ft_board_setup(void *blob, bd_t *bd) phys_addr_t base; phys_size_t size; + ft_cpu_setup(blob, bd); + /* limit the memory size to bank 1 until Linux can handle 40-bit PA */ base = getenv_bootm_low(); size = getenv_bootm_size(); diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 2bd5a47..4c258ca 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -45,14 +45,16 @@ #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ -/* SMP Definitions */ -#define CPU_RELEASE_ADDR CONFIG_SYS_INIT_SP_ADDR - #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL +/* + * SMP Definitions + */ +#define CPU_RELEASE_ADDR secondary_boot_func + /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 12000000 /* 12MHz */ @@ -167,6 +169,7 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) +#define CONFIG_ARCH_EARLY_INIT_R /* Physical Memory Map */ /* fixme: these need to be checked against the board */ -- 1.7.9.5