From mboxrd@z Thu Jan  1 00:00:00 1970
From: Chin Liang See <clsee@altera.com>
Date: Tue, 23 Sep 2014 05:20:19 -0500
Subject: [U-Boot] [WIP PATCH 0/2] arm: socfpga: Add Cadence QSPI support
In-Reply-To: <1411396109-20444-1-git-send-email-sr@denx.de>
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On Mon, 2014-09-22 at 16:28 +0200, ZY - sr wrote:
> Hi SoCFPGA-developers!
> 
> I'm currently using Marek's latest SoCFPGA port. This works really great so far.
> Thank you all for this effort.
> 
> What I need additionally is SPI NOR flash support. So I talked a bit with Marek
> and tried to port the Cadence QSPI driver to mainline U-Boot (on-top of Marek's
> patch set of course). This version in these patches now compiles clean. And
> detecting of the SPI flash also works good. Reading also seems to be okay.
> Only easing and writing have some problems.
> 
> Perhaps somebody from Altera with deeper Cadence SPI controller knowledge
> can take a quick look at this. Could be a pretty obvious mistake that I
> made while copying / porting the code. Or something else thats simply
> missing.
> 
> Any hints are really appretiated!
> 

Dear Stefan,

I can help to take a look as I was trying to upstream this code
previously. But it was later on hold as the SPI driver / framework is
under going some revamp. Hopefully I have some bandwidth tomorrow to
start looking into Marek and your patches.

Chin Liang


> BTW: I'm currently testing this on the EBV SoCrates board.
> 
> Thanks,
> Stefan
> 
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@altera.com>
> Cc: Vince Bridgers <vbridger@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Pavel Machek <pavel@denx.de>