[U-Boot] [PATCH 8/9] ARM: sunxi: Add support for using R_UART as console

Ian Campbell
2014-10-11T16:15:03Z

On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
> The A23 only has UART0 muxed with MMC0. Some of the boards we
> encountered expose R_UART as a set of pads.
>
> Add support for R_UART so we can have a console while using mmc.

I suppose R_UART is the h/w doc name. UARTR would fit the code better
but I suppose sticking with the h/w names is fine.

CONFIG_CONS_INDEX is also getting a bit out of hand, eventually we
should make it a Kconfig choice option.

> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Acked-by: Ian Campbell <ijc@hellion.org.uk>

> ---
> arch/arm/cpu/armv7/sunxi/board.c | 4 ++++
> arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 6 ++++++
> arch/arm/include/asm/arch-sunxi/cpu.h | 1 +
> arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++
> include/configs/sunxi-common.h | 1 +
> 5 files changed, 15 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
> index 61c1ba9..aeb2c2f 100644
> --- a/arch/arm/cpu/armv7/sunxi/board.c
> +++ b/arch/arm/cpu/armv7/sunxi/board.c
> @@ -75,6 +75,10 @@ int gpio_init(void)
> sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
> sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
> sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
> +#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_SUN8I)
> + sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX);
> + sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX);
> + sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
> #else
> #error Unsupported console port number. Please fix pin mux settings in board.c
> #endif
> diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
> index 8387b93..1eae976 100644
> --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
> +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
> @@ -13,6 +13,7 @@
> #include <common.h>
> #include <asm/io.h>
> #include <asm/arch/clock.h>
> +#include <asm/arch/prcm.h>
> #include <asm/arch/sys_proto.h>
>
> void clock_init_uart(void)
> @@ -20,6 +21,7 @@ void clock_init_uart(void)
> struct sunxi_ccm_reg *const ccm =
> (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>
> +#if CONFIG_CONS_INDEX < 5
> /* uart clock source is apb2 */
> writel(APB2_CLK_SRC_OSC24M|
> APB2_CLK_RATE_N_1|
> @@ -35,6 +37,10 @@ void clock_init_uart(void)
> setbits_le32(&ccm->apb2_reset_cfg,
> 1 << (APB2_RESET_UART_SHIFT +
> CONFIG_CONS_INDEX - 1));
> +#else
> + /* enable R_PIO and R_UART clocks, and de-assert resets */
> + prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
> +#endif
>
> /* Dup with clock_init_safe(), drop once sun6i SPL support lands */
> writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
> diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
> index 313e6c8..0de79a0 100644
> --- a/arch/arm/include/asm/arch-sunxi/cpu.h
> +++ b/arch/arm/include/asm/arch-sunxi/cpu.h
> @@ -111,6 +111,7 @@
> #define SUNXI_AVG_BASE 0x01ea0000
>
> #define SUNXI_PRCM_BASE 0x01f01400
> +#define SUNXI_R_UART_BASE 0x01f02800
> #define SUNXI_R_PIO_BASE 0x01f02c00
> #define SUNXI_P2WI_BASE 0x01f03400
>
> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
> index bbe815a..c216960 100644
> --- a/arch/arm/include/asm/arch-sunxi/gpio.h
> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
> @@ -164,6 +164,9 @@ enum sunxi_gpio_number {
>
> #define SUN4I_GPI4_SDC3 2
>
> +#define SUN8I_GPL2_R_UART_TX 2
> +#define SUN8I_GPL3_R_UART_RX 2
> +
> /* GPIO pin pull-up/down config */
> #define SUNXI_GPIO_PULL_DISABLE 0
> #define SUNXI_GPIO_PULL_UP 1
> diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
> index 7857a56..7e54296 100644
> --- a/include/configs/sunxi-common.h
> +++ b/include/configs/sunxi-common.h
> @@ -42,6 +42,7 @@
> #define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE
> #define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE
> #define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE
> +#define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE
>
> /* DRAM Base */
> #define CONFIG_SYS_SDRAM_BASE 0x40000000