From mboxrd@z Thu Jan 1 00:00:00 1970 From: Heiko Schocher Date: Thu, 30 Oct 2014 09:14:59 +0100 Subject: [U-Boot] [v2 PATCH 05/12] arm, at91: add missing ddr2 cr register MPDDRC_CR_EBISHARE define In-Reply-To: <1414656906-16632-1-git-send-email-hs@denx.de> References: <1414656906-16632-1-git-send-email-hs@denx.de> Message-ID: <1414656906-16632-6-git-send-email-hs@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Signed-off-by: Heiko Schocher --- Changes in v2: add comment from Andreas Biessmann: - rename "MPDDRC_CR_EBISHARE" to "MPDDRC_CR_DQMS_SHARED" arch/arm/include/asm/arch-at91/atmel_mpddrc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-at91/atmel_mpddrc.h b/arch/arm/include/asm/arch-at91/atmel_mpddrc.h index 5741f6e..130a85a 100644 --- a/arch/arm/include/asm/arch-at91/atmel_mpddrc.h +++ b/arch/arm/include/asm/arch-at91/atmel_mpddrc.h @@ -57,6 +57,7 @@ int ddr2_init(const unsigned int ram_address, #define ATMEL_MPDDRC_CR_DIC_DS (0x1 << 8) #define ATMEL_MPDDRC_CR_DIS_DLL (0x1 << 9) #define ATMEL_MPDDRC_CR_OCD_DEFAULT (0x7 << 12) +#define ATMEL_MPDDRC_CR_DQMS_SHARED (0x1 << 16) #define ATMEL_MPDDRC_CR_ENRDM_ON (0x1 << 17) #define ATMEL_MPDDRC_CR_NB_8BANKS (0x1 << 20) #define ATMEL_MPDDRC_CR_NDQS_DISABLED (0x1 << 21) -- 1.8.3.1