From: Stefan Roese <sr@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/4 v4] arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsi
Date: Fri, 7 Nov 2014 12:37:50 +0100 [thread overview]
Message-ID: <1415360272-13249-3-git-send-email-sr@denx.de> (raw)
In-Reply-To: <1415360272-13249-1-git-send-email-sr@denx.de>
This DT node is taken from the Rocketboard.org Linux repsitory. And
is needed to enable (configure) the Cadence DM SPI driver.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
---
arch/arm/dts/socfpga.dtsi | 15 +++++++++++++++
arch/arm/dts/socfpga_cyclone5_socrates.dts | 20 ++++++++++++++++++++
2 files changed, 35 insertions(+)
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 4472fd9..4a789a9 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -639,6 +639,21 @@
clock-names = "biu", "ciu";
};
+ qspi: spi at ff705000 {
+ compatible = "cadence,qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xff705000 0x1000>,
+ <0xffa00000 0x1000>;
+ interrupts = <0 151 4>;
+ clocks = <&qspi_clk>;
+ ext-decoder = <0>; /* external decoder */
+ num-chipselect = <4>;
+ fifo-depth = <128>;
+ bus-num = <2>;
+ status = "disabled";
+ };
+
/* Local timer */
timer at fffec600 {
compatible = "arm,cortex-a9-twd-timer";
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index a1814b4..9277174 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -48,3 +48,23 @@
&mmc {
status = "okay";
};
+
+&qspi {
+ status = "okay";
+
+ flash0: n25q00 at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q00";
+ reg = <0>; /* chip select */
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ page-size = <256>;
+ block-size = <16>; /* 2^16, 64KB */
+ read-delay = <4>; /* delay value in read data capture register */
+ tshsl-ns = <50>;
+ tsd2d-ns = <50>;
+ tchsh-ns = <4>;
+ tslch-ns = <4>;
+ };
+};
--
2.1.3
next prev parent reply other threads:[~2014-11-07 11:37 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-07 11:37 [U-Boot] [PATCH 0/4 v4] arm: socfpga: Add Cadence QSPI support Stefan Roese
2014-11-07 11:37 ` [U-Boot] [PATCH 1/4 v4] spi: Add Cadence QSPI DM driver used by SoCFPGA Stefan Roese
2014-11-07 15:04 ` Marek Vasut
2014-11-07 15:26 ` Stefan Roese
2014-11-07 19:56 ` Dinh Nguyen
2014-11-08 12:18 ` Stefan Roese
2014-12-06 12:56 ` Marek Vasut
2014-12-08 8:14 ` Stefan Roese
2016-01-14 2:17 ` Marek Vasut
2014-11-07 17:59 ` Simon Glass
2014-11-07 11:37 ` Stefan Roese [this message]
2014-11-07 17:21 ` [U-Boot] [PATCH 2/4 v4] arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsi Simon Glass
2014-11-07 17:26 ` Stefan Roese
2014-11-10 10:47 ` Pavel Machek
2014-11-10 15:48 ` Dinh Nguyen
2014-11-07 11:37 ` [U-Boot] [PATCH 3/4 v4] arm: socfpga: dts: Add spi0 alias for Cadence QSPI driver Stefan Roese
2014-11-07 15:06 ` Marek Vasut
2014-11-07 18:02 ` Simon Glass
2014-11-07 11:37 ` [U-Boot] [PATCH 4/4 v4] arm: socfpga: Add Cadence QSPI support to config header Stefan Roese
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