[U-Boot] [PATCH 1/2] mtd: nand: omap_gpmc: Add CONFIG_SYS_NAND_USE_READY to enable ready/busy

[Stefan Roese <sr@denx.de>]

By defining CONFIG_SYS_NAND_USE_READY the GPMC NAND driver makes
use of the ready pin / signal for busy / ready detection. This function
is already available but currently only used in SPL. I don't see a reason
to not use it in the main U-Boot as well. As it increases the NAND
performance.

I'm making it configurable, so that boards that might now have this pin
connected are still supported.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Roger Meier <r.meier@siemens.com>
Cc: Samuel Egli <samuel.egli@siemens.com>
---
 README                       |  5 +++++
 drivers/mtd/nand/omap_gpmc.c | 20 +++++++++++++++++---
 2 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/README b/README
index c3a9dfc..420c14b 100644
--- a/README
+++ b/README
@@ -4731,6 +4731,11 @@ Low Level (hardware related) configuration options:
 		- drivers/mtd/nand/ndfc.c
 		- drivers/mtd/nand/mxc_nand.c
 
+- CONFIG_SYS_NAND_USE_READY
+		Defined if a ready/busy pin is available on this board
+		which can be used to determine the state of the NAND
+		chip. Currently used on the OMAP/AM33xx NAND driver.
+
 - CONFIG_SYS_NDFC_EBC0_CFG
 		Sets the EBC0_CFG register for the NDFC. If not defined
 		a default value will be used.
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index 40d6705..8ca95d3 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -23,6 +23,16 @@
 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
 #define BCH4_BIT_PAD		4
 
+/*
+ * All OMAP / AM33xx SPL builds already use the ready / busy pin.
+ * So lets enable this new define to use this signal for SPL. This
+ * makes the check in the code easier since its reduced to a single
+ * macro.
+ */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NAND_USE_READY
+#endif
+
 #ifdef CONFIG_BCH
 static u8  bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
 				0x97, 0x79, 0xe5, 0x24, 0xb5};
@@ -73,9 +83,9 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
 		writeb(cmd, this->IO_ADDR_W);
 }
 
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_SYS_NAND_USE_READY
 /* Check wait pin as dev ready indicator */
-static int omap_spl_dev_ready(struct mtd_info *mtd)
+static int omap_dev_ready(struct mtd_info *mtd)
 {
 	return gpmc_cfg->status & (1 << 8);
 }
@@ -887,7 +897,11 @@ int board_nand_init(struct nand_chip *nand)
 		nand->read_buf = nand_read_buf16;
 	else
 		nand->read_buf = nand_read_buf;
-	nand->dev_ready = omap_spl_dev_ready;
 #endif
+
+#ifdef CONFIG_SYS_NAND_USE_READY
+	nand->dev_ready = omap_dev_ready;
+#endif
+
 	return 0;
 }
-- 
2.1.3