From mboxrd@z Thu Jan 1 00:00:00 1970 From: dinguyen at opensource.altera.com Date: Thu, 13 Nov 2014 11:23:41 -0600 Subject: [U-Boot] [PATCH v2] arm: socfpga: set skew settings for ethernet phy Message-ID: <1415899421-13816-1-git-send-email-dinguyen@opensource.altera.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Dinh Nguyen Set the PHY skew settings for the ethernet phy on the SOCFPGA Cyclone5 hardware. Signed-off-by: Dinh Nguyen Cc: Vince Bridgers Cc: Pavel Machek Cc: Marek Vasut Cc: Tom Rini Cc: Albert Aribaud Cc: Wolfgang Denk --- v2: Added comments on why it is necessary for setting the skew values. --- board/altera/socfpga/socfpga_cyclone5.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index 0f81d89..543a143 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -8,7 +8,9 @@ #include #include +#include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -39,3 +41,17 @@ int board_init(void) return 0; } + +int board_phy_config(struct phy_device *phydev) +{ + /* + * These skew settings for the KSZ9021 ethernet phy is required for ethernet + * to work reliably on most flavors of cyclone5 boards. + */ + ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, + 0x0); + ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, + 0x0); + ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, + 0xf0f0); +} -- 2.0.3