[U-Boot] [PATCH 03/13] ehci-mx5: Clean up

Benoît Thébaudeau
2012-11-05T20:10:27Z

Clean up ehci-mx5:
- Fix column alignments.
- Fix comments.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
.../drivers/usb/host/ehci-mx5.c | 34 ++++++++++----------
1 file changed, 17 insertions(+), 17 deletions(-)

diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
index 9a2c295..66ab25d 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
@@ -29,9 +29,9 @@
#define MX5_USBOTHER_REGS_OFFSET 0x800

-#define MXC_OTG_OFFSET 0
-#define MXC_H1_OFFSET 0x200
-#define MXC_H2_OFFSET 0x400
+#define MXC_OTG_OFFSET 0
+#define MXC_H1_OFFSET 0x200
+#define MXC_H2_OFFSET 0x400

#define MXC_USBCTRL_OFFSET 0
#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
@@ -40,23 +40,23 @@
#define MXC_USBH2CTRL_OFFSET 0x14

/* USB_CTRL */
-#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
-#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
-#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
-#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
-#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
+#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
+#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
+#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
+#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
+#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */

/* USB_PHY_CTRL_FUNC */
-#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
-#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
+#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
+#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */

/* USBH2CTRL */
-#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
-#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
-#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
+#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
+#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
+#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)

/* USB_CTRL_1 */
-#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
+#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)

/* USB pin configuration */
#define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
@@ -160,7 +160,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
}
break;
- case 1: /* Host 1 Host ULPI */
+ case 1: /* Host 1 ULPI */
#ifdef CONFIG_MX51
/* The clock for the USBH1 ULPI port will come externally
from the PHY. */
@@ -171,7 +171,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)

v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
- v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
+ v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused */
else
v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
@@ -187,7 +187,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
case 2: /* Host 2 ULPI */
v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
- v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
+ v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused */
else
v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */