[U-Boot] [U-Boot, 1/2, v4] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041

aneesh.bansal at freescale.com
2015-02-27T04:35:55Z

> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Thursday, February 26, 2015 3:43 AM
> To: Bansal Aneesh-B39320
> Cc: u-boot at lists.denx.de; Sun York-R58495; Gupta Ruchika-R66431
> Subject: Re: [U-Boot, 1/2, v4] powerpc/mpc85xx: SECURE BOOT- NAND
> secure boot target for P3041
>
> [Reposting comment on v4 as York requested]
>
> On Wed, Feb 25, 2015 at 02:17:56PM +0530, Aneesh Bansal wrote:
> > diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
> > b/arch/powerpc/cpu/mpc85xx/cpu_init.c
> > index 4cf8853..ef56cc0 100644
> > --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
> > +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
> > @@ -843,6 +843,23 @@ int cpu_init_r(void)
> > setup_mp();
> > #endif
> >
> > +#if defined(CONFIG_SYS_RAMBOOT) &&
> defined(CONFIG_SYS_INIT_L3_ADDR) && \
> > + defined(CONFIG_SECURE_BOOT)
> > + /* Disable the TLB Created for L3 and create the TLB required for
> > + * PCIE (CONFIG_SYS_PCIE1_MEM_VIRT) which was not created
> earlier.
> > + */
> > + int tlb_index;
> > + tlb_index = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
> > + if (tlb_index != -1) {
> > + disable_tlb(tlb_index);
> > +
> > + set_tlb(1, CONFIG_SYS_PCIE1_MEM_VIRT,
> > + CONFIG_SYS_PCIE1_MEM_PHYS,
> > + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> > + 0, tlb_index, BOOKE_PAGESZ_1G, 1);
> > + }
> > +#endif
>
> Why are you assuming in generic 85xx code that the TLB for PCIE1 needs to
> be created? e500mc should have enough TLB1 entries that you don't need to
> share (or if it's due to address conflicts, a board may have PCI at a different
> address), and PCI may not exist at all on some boards.
>
> -Scott

TLB's are created in freescale/common/p_corenet/tlb.c
In case of Secure Boot, L3 is used as 1M SRAM and the address of the SRAM is at 0xbff00000.
The PCIE TLB entry conflicts with the above entry and so the entry for PCIE was not created
at that point of time.
This is why it is being created here in cpu_init_r() when U-Boot has relocated to DDR and the
TLB entry for SRAM is not required.
Proper comments have been added in tlb.c to explain why it is being done.
If address for PCI is changed than this also will have to be taken care of.
The code is protected by relevant macros (CONFIG_SYS_RAMBOOT, CONFIG_SYS_INIT_L3_ADDR,
CONFIG_SECURE_BOOT)