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From: Scott Wood <scottwood@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v8 24/28] armv8/ls2085aqds: NAND boot support
Date: Tue, 24 Mar 2015 14:49:56 -0500	[thread overview]
Message-ID: <1427226596.22867.63.camel@freescale.com> (raw)
In-Reply-To: <1427226456-3944-1-git-send-email-yorksun@freescale.com>

On Tue, 2015-03-24 at 12:47 -0700, York Sun wrote:
> +Booting from NAND
> +-------------------
> +Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
> +The difference between NAND boot RCW image and NOR boot image is the PBI
> +command sequence. Below is one example for PBI commands for QDS.
> +
> +1) CCSR 4-byte write to 0x00e00404, data=0x00000000
> +2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
> +The above two commands set bootloc register to 0x00000000_1800a000 where
> +the u-boot code will be running in OCRAM.
> +
> +3) Block Copy: SRC=0x0107, SRC_ADDR=0x00100000, DEST_ADDR=0x1800a000,
> +BLOCK_SIZE=0x00014000
> +This command copies u-boot image from NAND device into OCRAM. The values need
> +to adjust accordingly.
> +
> +SRC		should match the cfg_rcw_src, the reset config pins. It depends
> +		on the NAND device. See reference manual for cfg_rcw_src.
> +SRC_ADDR	is the offset of u-boot image in NAND device. It should match
> +		CONFIG_SYS_NAND_U_BOOT_OFFS. In the example above, it is 1MB.

Why 1 MiB?

-Scott

  parent reply	other threads:[~2015-03-24 19:49 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-24 19:47 [U-Boot] [PATCH v8 24/28] armv8/ls2085aqds: NAND boot support York Sun
2015-03-24 19:47 ` [U-Boot] [PATCH v8 26/28] armv8/ls2085ardb: Enable NAND SPL support York Sun
2015-03-24 19:49 ` Scott Wood [this message]
2015-03-24 19:55   ` [U-Boot] [PATCH v8 24/28] armv8/ls2085aqds: NAND boot support York Sun

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