From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Date: Fri, 27 Mar 2015 14:04:53 +0000 Subject: [U-Boot] [PATCH 1/3] sunxi: sun4i: add missing 912MHz clock divisors In-Reply-To: <5514A013.7040300@gmail.com> References: <5514A013.7040300@gmail.com> Message-ID: <1427465093.13935.151.camel@hellion.org.uk> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Fri, 2015-03-27 at 00:10 +0000, Iain Paton wrote: > clock divisors table was missing an entry for 912MHz. The same table is > used for sun7i where the default boot clock is 912MHz, resulting in A20 > boards being overclocked to 960MHz Apart from the missing entry, should it not be the case that we pick the highest frequency <= than the requested frequency, rather than the next available (potentially higher) frequency? IOW I'd expect things to be underclocked@768MHz without this change, which would mean that clock_set_pll1 is buggy. Ian. > > Signed-off-by: Iain Paton > --- > arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c > index 49f4032..c720e96 100644 > --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c > +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c > @@ -102,6 +102,7 @@ static struct { > /* This array must be ordered by frequency. */ > { PLL1_CFG(16, 0, 0, 0), 384000000 }, > { PLL1_CFG(16, 1, 0, 0), 768000000 }, > + { PLL1_CFG(19, 1, 0, 0), 912000000 }, > { PLL1_CFG(20, 1, 0, 0), 960000000 }, > { PLL1_CFG(21, 1, 0, 0), 1008000000}, > { PLL1_CFG(22, 1, 0, 0), 1056000000},