From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexey Brodkin Date: Fri, 3 Apr 2015 16:27:36 +0000 Subject: [U-Boot] [PATCH] arc: add support for SLC (System Level Cache, AKA L2-cache) In-Reply-To: <1427797512-32080-1-git-send-email-abrodkin@synopsys.com> References: <1427797512-32080-1-git-send-email-abrodkin@synopsys.com> Message-ID: <1428078455.2836.21.camel@synopsys.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Tue, 2015-03-31 at 13:25 +0300, Alexey Brodkin wrote: > ARCv2 cores may have built-in SLC (System Level Cache, AKA L2-cache). > This change adds functions required for controlling SLC: > * slc_enable/disable > * slc_flush/invalidate > > For now we just disable SLC to escape DMA coherency issues until either: > * SLC flush/invalidate is supported in DMA APIin U-Boot > * hardware DMA coherency is implemented (that might be board specific > so probably we'll need to have a separate Kconfig option for > controlling SLC explicitly) > > Signed-off-by: Alexey Brodkin Applied, thanks. -Alexey