From: Marcel Ziswiler <marcel@ziswiler.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/2] Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.
Date: Tue, 04 Aug 2015 10:32:43 +0200 [thread overview]
Message-ID: <1438677163.2798.7.camel@ziswiler.com> (raw)
In-Reply-To: <1438200801-10888-2-git-send-email-twarren@nvidia.com>
On Wed, 2015-07-29 at 13:13 -0700, Tom Warren wrote:
> Added PLL variables (dividers mask/shift, lock enable/detect, etc.)
> to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X.
>
> Used pllinfo struct in all clock functions, validated on T210.
> Should be equivalent to prior code on T124/114/30/20 but needs test.
>
> Corrections to divm mask vs shift and T20/30 divN masks thanks to
> Marcel Ziswiler.
>
> Signed-off-by: Tom Warren <twarren@nvidia.com>
While this boots on Colibri T20/T30 as well as Apalis T30 there is
still something askew on T20 as e.g. USB Ethernet is more than 6 times
slower than before. T30 on the other hand seems to work fine. I will
try to find some time to investigate further.
next prev parent reply other threads:[~2015-08-04 8:32 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-29 20:13 [U-Boot] [PATCH 1/2] Tegra: clocks: Add 38.4MHz OSC support for T210 use Tom Warren
2015-07-29 20:13 ` [U-Boot] [PATCH 2/2] Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc Tom Warren
2015-08-04 8:32 ` Marcel Ziswiler [this message]
2015-08-04 15:36 ` Tom Warren
2015-08-05 14:19 ` Marcel Ziswiler
2015-08-10 12:58 ` Simon Glass
2015-07-30 18:41 ` [U-Boot] [PATCH 1/2] Tegra: clocks: Add 38.4MHz OSC support for T210 use Stephen Warren
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