From: Marcel Ziswiler <marcel@ziswiler.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/2] Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.
Date: Wed, 05 Aug 2015 16:19:50 +0200 [thread overview]
Message-ID: <1438784390.2747.4.camel@ziswiler.com> (raw)
In-Reply-To: <b169b19351724aa1bca8fd9dc093a3d2@HQMAIL104.nvidia.com>
On Tue, 2015-08-04 at 15:36 +0000, Tom Warren wrote:
> Thanks. My T20/T30 boards are moth-balled, so I don't test on them.
> T210 USB is fine.
> If you can provide CAR register dumps (0x60006000 - 0x60006FFF) on
> T20 I can take a look.
I had a look at it. Looks like you missed the cpcon stuff for PLLX both
on T20 as well as T30 but while the former's PLLX won't even lock any
more the later seems to still lock OK. Nonetheless I will send a patch
to fix this for both shortly.
> Appreciate any testing you can do. This won't go in to u-boot-tegra
> until you are satisified.
Your patience with us remaining T20/T30 users is highly appreciated as
we still hope to be selling those Colibris for another 10 resp. 13
years!
next prev parent reply other threads:[~2015-08-05 14:19 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-29 20:13 [U-Boot] [PATCH 1/2] Tegra: clocks: Add 38.4MHz OSC support for T210 use Tom Warren
2015-07-29 20:13 ` [U-Boot] [PATCH 2/2] Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc Tom Warren
2015-08-04 8:32 ` Marcel Ziswiler
2015-08-04 15:36 ` Tom Warren
2015-08-05 14:19 ` Marcel Ziswiler [this message]
2015-08-10 12:58 ` Simon Glass
2015-07-30 18:41 ` [U-Boot] [PATCH 1/2] Tegra: clocks: Add 38.4MHz OSC support for T210 use Stephen Warren
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