From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peng Fan Date: Wed, 12 Aug 2015 17:40:46 +0800 Subject: [U-Boot] [PATCH V2 2/3] net: fec: do not access reserved register for i.MX6UL In-Reply-To: <1439372447-7352-1-git-send-email-Peng.Fan@freescale.com> References: <1439372447-7352-1-git-send-email-Peng.Fan@freescale.com> Message-ID: <1439372447-7352-2-git-send-email-Peng.Fan@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de The MIB RAM and FIFO receive start register does not exist on i.MX6UL. Accessing these register will cause enet not work well. Signed-off-by: Peng Fan Signed-off-by: Fugang Duan Cc: Joe Hershberger Cc: Stefano Babic --- Changes v2: Using runtime check, but not hardcoding "#ifdef". This patch depends on the runtime checking patch: https://patchwork.ozlabs.org/patch/505621/. drivers/net/fec_mxc.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index c5dcbbb..bff5fd1 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -17,6 +17,7 @@ #include #include +#include #include #include #include @@ -551,12 +552,15 @@ static int fec_init(struct eth_device *dev, bd_t* bd) writel(0x00000000, &fec->eth->gaddr2); - /* clear MIB RAM */ - for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) - writel(0, i); + /* Do not access reserved register for i.MX6UL */ + if (!is_cpu_type(MXC_CPU_MX6UL)) { + /* clear MIB RAM */ + for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) + writel(0, i); - /* FIFO receive start register */ - writel(0x520, &fec->eth->r_fstart); + /* FIFO receive start register */ + writel(0x520, &fec->eth->r_fstart); + } /* size and address of each buffer */ writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); -- 1.8.4