From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Date: Mon, 17 Aug 2015 09:29:29 +0100 Subject: [U-Boot] [PATCH 11/15] sunxi_nand_spl: Add support for sun4i and sun5i SoCs In-Reply-To: <1439668968-3882-12-git-send-email-hdegoede@redhat.com> References: <1439668968-3882-1-git-send-email-hdegoede@redhat.com> <1439668968-3882-12-git-send-email-hdegoede@redhat.com> Message-ID: <1439800169.3480.64.camel@hellion.org.uk> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote: > Other then having a few less chip-select lines the nand controller > on sun4i, sun5i and sun7i is identical. > > Signed-off-by: Hans de Goede > --- > board/sunxi/board.c | 12 +++++++++--- > drivers/mtd/nand/Kconfig | 4 ++-- > 2 files changed, 11 insertions(+), 5 deletions(-) > > diff --git a/board/sunxi/board.c b/board/sunxi/board.c > index 1ebd0a4..d411e96 100644 > --- a/board/sunxi/board.c > +++ b/board/sunxi/board.c > @@ -112,13 +112,19 @@ int dram_init(void) > static void nand_pinmux_setup(void) > { > unsigned int pin; > - for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(6); pin++) > - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); > > - for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(22); pin++) > + for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) This looks to have added GPC(7) to all platforms, was that intentional? Ian.