From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chin Liang See Date: Thu, 20 Aug 2015 19:54:15 -0500 Subject: [U-Boot] [PATCH v2 2/2] arm: socfpga: config: Remove hard-coded drvsel and smpsel In-Reply-To: <1440055132-2290-1-git-send-email-clsee@altera.com> References: <1440055132-2290-1-git-send-email-clsee@altera.com> Message-ID: <1440118455.2020.1.camel@clsee-VirtualBox> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi guys, Any comment or ack for this patch? Thanks Chin Liang On Thu, 2015-08-20 at 02:18 -0500, Chin Liang See wrote: > Remove hard-coded SDMMC timing parameter drvsel and smplsel. > This setting now will come from SDMMC calibration > > Signed-off-by: Chin Liang See > Cc: Dinh Nguyen > Cc: Pavel Machek > Cc: Marek Vasut > Cc: Stefan Roese > --- > Changes for v2 > - Update the CC list > --- > include/configs/socfpga_common.h | 2 -- > 1 files changed, 0 insertions(+), 2 deletions(-) > > diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h > index c64c7ed..1a070fd 100644 > --- a/include/configs/socfpga_common.h > +++ b/include/configs/socfpga_common.h > @@ -155,8 +155,6 @@ > #define CONFIG_DWMMC > #define CONFIG_SOCFPGA_DWMMC > #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 > -#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 > -#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 > /* FIXME */ > /* using smaller max blk cnt to avoid flooding the limited stack we have */ > #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */