[U-Boot] [PATCH 1/3][v2] Pointers in ESBC header made 32 bit

[U-Boot] [PATCH 1/3][v2] Pointers in ESBC header made 32 bit

[Aneesh Bansal]

For the Chain of Trust, the esbc_validate command supports
32 bit fields for location of the image. In the header structure
definition, these were declared as pointers which made them
64 bit on a 64 bit core.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
---
Changes in v2:
Compile time warning removed when printing Header Address.

 board/freescale/common/fsl_validate.c | 20 ++++++++++----------
 include/fsl_validate.h                | 14 +++++++-------
 2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c
index 5283648..465676f 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -63,12 +63,12 @@ static u32 check_ie(struct fsl_secboot_img_priv *img)
  * address
  */
 #if defined(CONFIG_MPC85xx)
-int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
+int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
 	u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE);
-	ulong flash_addr, addr;
+	u32 flash_addr, addr;
 	int found = 0;
 	int i = 0;
 
@@ -76,7 +76,7 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
 		flash_addr = flash_info[i].start[0];
 		addr = flash_info[i].start[0] + csf_flash_offset;
 		if (memcmp((u8 *)addr, barker_code, ESBC_BARKER_LEN) == 0) {
-			debug("Barker found on addr %lx\n", addr);
+			debug("Barker found on addr %x\n", addr);
 			found = 1;
 			break;
 		}
@@ -94,7 +94,7 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
 /* For platforms like LS1020, correct flash address is present in
  * the header. So the function reqturns flash base address as 0
  */
-int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
+int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
@@ -108,11 +108,11 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
 }
 #endif
 
-static int get_ie_info_addr(ulong *ie_addr)
+static int get_ie_info_addr(u32 *ie_addr)
 {
 	struct fsl_secboot_img_hdr *hdr;
 	struct fsl_secboot_sg_table *sg_tbl;
-	ulong flash_base_addr, csf_addr;
+	u32 flash_base_addr, csf_addr;
 
 	if (get_csf_base_addr(&csf_addr, &flash_base_addr))
 		return -1;
@@ -127,11 +127,11 @@ static int get_ie_info_addr(ulong *ie_addr)
 	 */
 #if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET)
 	sg_tbl = (struct fsl_secboot_sg_table *)
-		 (((ulong)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
+		 (((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
 		  flash_base_addr);
 #else
 	sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr +
-						 (ulong)hdr->psgtable);
+						 (u32)hdr->psgtable);
 #endif
 
 	/* IE Key Table is the first entry in the SG Table */
@@ -142,7 +142,7 @@ static int get_ie_info_addr(ulong *ie_addr)
 	*ie_addr = sg_tbl->src_addr;
 #endif
 
-	debug("IE Table address is %lx\n", *ie_addr);
+	debug("IE Table address is %x\n", *ie_addr);
 	return 0;
 }
 
@@ -549,7 +549,7 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img)
 	if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN))
 		return ERROR_ESBC_CLIENT_HEADER_BARKER;
 
-	sprintf(buf, "%p", hdr->pimg);
+	sprintf(buf, "%x", hdr->pimg);
 	setenv("img_addr", buf);
 
 	if (!hdr->img_size)
diff --git a/include/fsl_validate.h b/include/fsl_validate.h
index c460534..92dd98b 100644
--- a/include/fsl_validate.h
+++ b/include/fsl_validate.h
@@ -82,14 +82,14 @@ struct fsl_secboot_img_hdr {
 	u32 psign;		/* signature offset */
 	u32 sign_len;		/* length of the signature in bytes */
 	union {
-		struct fsl_secboot_sg_table *psgtable;	/* ptr to SG table */
-		u8 *pimg;	/* ptr to ESBC client image */
+		u32 psgtable;	/* ptr to SG table */
+		u32 pimg;	/* ptr to ESBC client image */
 	};
 	union {
 		u32 sg_entries;	/* no of entries in SG table */
 		u32 img_size;	/* ESBC client image size in bytes */
 	};
-	ulong img_start;		/* ESBC client entry point */
+	u32 img_start;		/* ESBC client entry point */
 	u32 sg_flag;		/* Scatter gather flag */
 	u32 uid_flag;
 	u32 fsl_uid_0;
@@ -133,7 +133,7 @@ struct srk_table {
  */
 struct fsl_secboot_sg_table {
 	u32 len;		/* length of the segment in bytes */
-	ulong src_addr;		/* ptr to the data segment */
+	u32 src_addr;		/* ptr to the data segment */
 };
 #else
 /*
@@ -146,8 +146,8 @@ struct fsl_secboot_sg_table {
 struct fsl_secboot_sg_table {
 	u32 len;
 	u32 trgt_id;
-	ulong src_addr;
-	ulong dst_addr;
+	u32 src_addr;
+	u32 dst_addr;
 };
 #endif
 
@@ -162,7 +162,7 @@ struct fsl_secboot_sg_table {
  */
 struct fsl_secboot_img_priv {
 	uint32_t hdr_location;
-	ulong ie_addr;
+	u32 ie_addr;
 	u32 key_len;
 	struct fsl_secboot_img_hdr hdr;
 
-- 
1.8.1.4

[U-Boot] [PATCH 2/3][v2] Data types defined for 64 bit physical address

[Aneesh Bansal]

Data types and I/O functions have been defined for
64 bit physical addresses in arm.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
---
Changes in v2:
There is no need for defining 64 bit I/O operations.
If an IP needs to do 64 bit access, it will do it by defining
32 bit addr_hi and addr_lo.

 arch/arm/include/asm/types.h | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
index ee77c41..d87f955 100644
--- a/arch/arm/include/asm/types.h
+++ b/arch/arm/include/asm/types.h
@@ -45,12 +45,15 @@ typedef unsigned long long u64;
 #define BITS_PER_LONG 32
 #endif	/* CONFIG_ARM64 */
 
-/* Dma addresses are 32-bits wide.  */
-
+#ifdef CONFIG_PHYS_64BIT
+typedef u64 dma_addr_t;
+typedef u64 phys_addr_t;
+typedef u64 phys_size_t;
+#else
 typedef u32 dma_addr_t;
-
-typedef unsigned long phys_addr_t;
-typedef unsigned long phys_size_t;
+typedef u32 phys_addr_t;
+typedef u32 phys_size_t;
+#endif
 
 #endif /* __KERNEL__ */
 
-- 
1.8.1.4

[U-Boot] [PATCH 3/3][v2] crypto/fsl: SEC driver cleanup for 64 bit and endianness

[Aneesh Bansal]

The SEC driver code has been cleaned up to work for 64 bit
physical addresses and systems where endianess of SEC block
is different from the Core.
Changes:
1. Descriptor created on Core is modified as per SEC block
   endianness before the job is submitted.
2. The read/write of physical addresses to Job Rings are done
   using I/O functions defined for SEC which will take care of
   the endianness.
3. The 32 bit low and high part of the 64 bit address in
   descriptor will vary depending on endianness of SEC.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
---
Changes in v2:
sec_out_phys and sec_in_phys has been defined in fsl_sec.h
to do two 32 bit write or read opeartions.
The low and high part of the 32 bit address will depend on
endianness of CAAM Block.

 drivers/crypto/fsl/desc_constr.h | 24 ++++++++++++++++++++++++
 drivers/crypto/fsl/jr.c          | 32 ++++++++++++++++++++++----------
 drivers/crypto/fsl/jr.h          |  3 +--
 include/fsl_sec.h                | 28 ++++++++++++++++++++++++++++
 4 files changed, 75 insertions(+), 12 deletions(-)

diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h
index f9cae91..ac4a933 100644
--- a/drivers/crypto/fsl/desc_constr.h
+++ b/drivers/crypto/fsl/desc_constr.h
@@ -36,6 +36,21 @@
 			       LDST_SRCDST_WORD_DECOCTRL | \
 			       (LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT))
 
+#ifdef CONFIG_PHYS_64BIT
+union ptr_addr_t {
+	u64 m_whole;
+	struct {
+#ifdef CONFIG_SYS_FSL_SEC_LE
+		u32 low;
+		u32 high;
+#else
+		u32 high;
+		u32 low;
+#endif
+	} m_halfs;
+};
+#endif
+
 static inline int desc_len(u32 *desc)
 {
 	return *desc & HDR_DESCLEN_MASK;
@@ -65,7 +80,16 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr)
 {
 	dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
 
+#ifdef CONFIG_PHYS_64BIT
+	/* The Position of low and high part of 64 bit address
+	 * will depend on the endianness of CAAM Block */
+	union ptr_addr_t ptr_addr;
+	ptr_addr.m_halfs.high = (u32)(ptr >> 32);
+	ptr_addr.m_halfs.low = (u32)ptr;
+	*offset = ptr_addr.m_whole;
+#else
 	*offset = ptr;
+#endif
 
 	(*desc) += CAAM_PTR_SZ / CAAM_CMD_SZ;
 }
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 17392c9..07b97e8 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -11,6 +11,7 @@
 #include "fsl_sec.h"
 #include "jr.h"
 #include "jobdesc.h"
+#include "desc_constr.h"
 
 #define CIRC_CNT(head, tail, size)	(((head) - (tail)) & (size - 1))
 #define CIRC_SPACE(head, tail, size)	CIRC_CNT((tail), (head) + 1, (size))
@@ -154,11 +155,25 @@ static int jr_hw_reset(void)
 
 /* -1 --- error, can't enqueue -- no space available */
 static int jr_enqueue(uint32_t *desc_addr,
-	       void (*callback)(uint32_t desc, uint32_t status, void *arg),
+	       void (*callback)(uint32_t status, void *arg),
 	       void *arg)
 {
 	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
 	int head = jr.head;
+	uint32_t desc_word;
+	int length = desc_len(desc_addr);
+	int i;
+
+	/* The descriptor must be submitted to SEC block as per endianness
+	 * of the SEC Block.
+	 * So, if the endianness of Core and SEC block is different, each word
+	 * of the descriptor will be byte-swapped.
+	 */
+	for (i = 0; i < length; i++) {
+		desc_word = desc_addr[i];
+		sec_out32((uint32_t *)&desc_addr[i], desc_word);
+	}
+
 	dma_addr_t desc_phys_addr = virt_to_phys(desc_addr);
 
 	if (sec_in32(&regs->irsa) == 0 ||
@@ -166,7 +181,6 @@ static int jr_enqueue(uint32_t *desc_addr,
 		return -1;
 
 	jr.info[head].desc_phys_addr = desc_phys_addr;
-	jr.info[head].desc_addr = (uint32_t)desc_addr;
 	jr.info[head].callback = (void *)callback;
 	jr.info[head].arg = arg;
 	jr.info[head].op_done = 0;
@@ -177,7 +191,7 @@ static int jr_enqueue(uint32_t *desc_addr,
 					ARCH_DMA_MINALIGN);
 	flush_dcache_range(start, end);
 
-	jr.input_ring[head] = desc_phys_addr;
+	sec_out_phys(&jr.input_ring[head], desc_phys_addr);
 	start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
 	end = ALIGN(start + sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
 	flush_dcache_range(start, end);
@@ -195,7 +209,7 @@ static int jr_dequeue(void)
 	int head = jr.head;
 	int tail = jr.tail;
 	int idx, i, found;
-	void (*callback)(uint32_t desc, uint32_t status, void *arg);
+	void (*callback)(uint32_t status, void *arg);
 	void *arg = NULL;
 
 	while (sec_in32(&regs->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) {
@@ -208,14 +222,12 @@ static int jr_dequeue(void)
 
 		found = 0;
 
-		dma_addr_t op_desc = jr.output_ring[jr.tail].desc;
-		uint32_t status = jr.output_ring[jr.tail].status;
-		uint32_t desc_virt;
+		dma_addr_t op_desc = sec_in_phys(&jr.output_ring[jr.tail].desc);
+		uint32_t status = sec_in32(&jr.output_ring[jr.tail].status);
 
 		for (i = 0; CIRC_CNT(head, tail + i, jr.size) >= 1; i++) {
 			idx = (tail + i) & (jr.size - 1);
 			if (op_desc == jr.info[idx].desc_phys_addr) {
-				desc_virt = jr.info[idx].desc_addr;
 				found = 1;
 				break;
 			}
@@ -244,13 +256,13 @@ static int jr_dequeue(void)
 		sec_out32(&regs->orjr, 1);
 		jr.info[idx].op_done = 0;
 
-		callback(desc_virt, status, arg);
+		callback(status, arg);
 	}
 
 	return 0;
 }
 
-static void desc_done(uint32_t desc, uint32_t status, void *arg)
+static void desc_done(uint32_t status, void *arg)
 {
 	struct result *x = arg;
 	x->status = status;
diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
index 1526060..5f15ed5 100644
--- a/drivers/crypto/fsl/jr.h
+++ b/drivers/crypto/fsl/jr.h
@@ -42,9 +42,8 @@ struct op_ring {
 } __packed;
 
 struct jr_info {
-	void (*callback)(dma_addr_t desc, uint32_t status, void *arg);
+	void (*callback)(uint32_t status, void *arg);
 	dma_addr_t desc_phys_addr;
-	uint32_t desc_addr;
 	uint32_t desc_len;
 	uint32_t op_done;
 	void *arg;
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index abc62da..9f344a8 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -28,6 +28,34 @@
 #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
 #endif
 
+#ifdef CONFIG_PHYS_64BIT
+#ifdef CONFIG_SYS_FSL_SEC_LE
+
+#define sec_in_phys(addr)					\
+	((u64)sec_in32((u32 *)(addr) + 1) << 32) |		\
+	(sec_in32((u32 *)(addr)))
+
+#define sec_out_phys(addr, val)					\
+	sec_out32((u32 *)(addr) + 1, (u32)((val) >> 32));	\
+	sec_out32((u32 *)(addr), (u32)(val))
+
+#elif defined(CONFIG_SYS_FSL_SEC_BE)
+
+#define sec_in_phys(addr)					\
+	((u64)sec_in32((u32 *)(addr)) << 32) |			\
+	(sec_in32((u32 *)(addr) + 1))
+
+#define sec_out_phys(addr, val)					\
+	sec_out32((u32 *)(addr), (u32)((val) >> 32));		\
+	sec_out32((u32 *)(addr) + 1, (u32)(val))
+
+#else
+#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
+#endif
+#else
+#define sec_out_phys	sec_out32
+#define sec_in_phys	sec_in32
+#endif
 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
 /* RNG4 TRNG test registers */
-- 
1.8.1.4