From: Jagan Teki <jteki@openedev.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v4 16/16] spi: zynq_spi: Store cs value into private data
Date: Tue, 1 Sep 2015 11:41:47 +0530 [thread overview]
Message-ID: <1441087907-25993-17-git-send-email-jteki@openedev.com> (raw)
In-Reply-To: <1441087907-25993-1-git-send-email-jteki@openedev.com>
Store cs value into private data and use it while activating
chipselect instead of passing through function.
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
drivers/spi/zynq_spi.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 70d7716..70ddd7f 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -61,6 +61,7 @@ struct zynq_spi_platdata {
/* zynq spi priv */
struct zynq_spi_priv {
struct zynq_spi_regs *regs;
+ u8 cs;
u8 mode;
u8 fifo_depth;
u32 freq; /* required frequency */
@@ -128,7 +129,7 @@ static int zynq_spi_probe(struct udevice *bus)
return 0;
}
-static void spi_cs_activate(struct udevice *dev, uint cs)
+static void spi_cs_activate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
struct zynq_spi_priv *priv = dev_get_priv(bus);
@@ -143,7 +144,7 @@ static void spi_cs_activate(struct udevice *dev, uint cs)
* xx01 - cs1
* x011 - cs2
*/
- cr |= (~(0x1 << cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
+ cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
writel(cr, ®s->cr);
}
@@ -199,8 +200,9 @@ static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
return -1;
}
+ priv->cs = slave_plat->cs;
if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(dev, slave_plat->cs);
+ spi_cs_activate(dev);
while (rx_len > 0) {
/* Write the data into TX FIFO - tx threshold is fifo_depth */
--
1.9.1
next prev parent reply other threads:[~2015-09-01 6:11 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-01 6:11 [U-Boot] [PATCH v4 00/16] spi: zynq qspi support Jagan Teki
2015-09-01 6:11 ` [U-Boot] [PATCH v4 01/16] spi: Add zynq qspi controller driver Jagan Teki
2015-09-03 7:26 ` Siva Durga Prasad Paladugu
2015-09-03 8:07 ` Jagan Teki
2015-09-03 8:38 ` Siva Durga Prasad Paladugu
2015-09-03 9:47 ` Jagan Teki
2015-09-04 11:38 ` Siva Durga Prasad Paladugu
2015-10-13 12:22 ` Hannes Schmelzer
2015-10-15 8:39 ` Hannes Schmelzer
2015-11-05 7:33 ` Hannes Schmelzer
2015-11-05 7:56 ` Jagan Teki
2015-09-01 6:11 ` [U-Boot] [PATCH v4 02/16] dts: zynq: Add zynq qspi controller nodes Jagan Teki
2015-09-01 6:11 ` [U-Boot] [PATCH v4 03/16] doc: device-tree-bindings: spi: Add zynq qspi info Jagan Teki
2015-09-01 6:11 ` [U-Boot] [PATCH v4 04/16] dts: microzed: Enable zynq qspi controller node Jagan Teki
2015-09-01 6:11 ` [U-Boot] [PATCH v4 05/16] dts: zc702: " Jagan Teki
2015-09-01 6:11 ` [U-Boot] [PATCH v4 06/16] dts: zc706: " Jagan Teki
2015-09-01 6:11 ` [U-Boot] [PATCH v4 07/16] dts: zc770-xm010: " Jagan Teki
2015-09-01 8:22 ` Michal Simek
2015-09-01 8:43 ` Jagan Teki
2015-09-01 9:00 ` Michal Simek
2015-09-01 6:11 ` [U-Boot] [PATCH v4 08/16] dts: zed: " Jagan Teki
2015-09-01 6:11 ` [U-Boot] [PATCH v4 09/16] configs: Enable legacy SPI flash interface support Jagan Teki
2015-09-01 6:11 ` [U-Boot] [PATCH v4 10/16] zynq-common: Enable zynq qspi controller support Jagan Teki
2015-09-01 8:19 ` Michal Simek
2015-09-01 6:11 ` [U-Boot] [PATCH v4 11/16] zynq-common: Enable Bank/Extended address register support Jagan Teki
2015-09-01 6:11 ` [U-Boot] [PATCH v4 12/16] configs: zynq: Enable zynq qspi controller Jagan Teki
2015-09-01 6:11 ` [U-Boot] [PATCH v4 13/16] spi: Kconfig: Add Zynq QSPI controller entry Jagan Teki
2015-09-01 8:18 ` Michal Simek
2015-09-01 6:11 ` [U-Boot] [PATCH v4 14/16] spi: zynq_spi: Add config reg shift named macros Jagan Teki
2015-09-01 6:11 ` [U-Boot] [PATCH v4 15/16] spi: zynq_spi: Rename baudrate divisor mask name Jagan Teki
2015-09-01 6:11 ` Jagan Teki [this message]
2015-09-01 6:14 ` [U-Boot] [PATCH v4 00/16] spi: zynq qspi support Jagan Teki
2015-09-01 8:23 ` Michal Simek
2015-09-04 12:33 ` Jagan Teki
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