From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chin Liang See Date: Tue, 1 Sep 2015 04:14:49 -0500 Subject: [U-Boot] [PATCH] spi: cadence_qspi: Ensure spi_calibration is run when sclk change In-Reply-To: <1441098818.1901.4.camel@clsee-VirtualBox> References: <1441097207-2162-1-git-send-email-clsee@altera.com> <201509011101.55689.marex@denx.de> <1441098818.1901.4.camel@clsee-VirtualBox> Message-ID: <1441098889.1901.5.camel@clsee-VirtualBox> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Tue, 2015-09-01 at 04:13 -0500, Chin Liang See wrote: > On Tue, 2015-09-01 at 11:01 +0200, marex at denx.de wrote: > > On Tuesday, September 01, 2015 at 10:46:47 AM, Chin Liang See wrote: > > > Ensuring spi_calibration is run when there is a change of sclk > > > frequency. This will ensure the qspi flash access works for high > > > sclk frequency > > > > > > Signed-off-by: Chin Liang See > > > Cc: Dinh Nguyen > > > Cc: Marek Vasut > > > Cc: Stefan Roese > > > Cc: Vikas Manocha > > > Cc: Jagannadh Teki > > > Cc: Pavel Machek > > > --- > > > drivers/spi/cadence_qspi.c | 3 +++ > > > 1 files changed, 3 insertions(+), 0 deletions(-) > > > > > > diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c > > > index 34a0f46..512bf2d 100644 > > > --- a/drivers/spi/cadence_qspi.c > > > +++ b/drivers/spi/cadence_qspi.c > > > @@ -128,6 +128,9 @@ static int cadence_spi_set_speed(struct udevice *bus, > > > uint hz) > > > > > > cadence_spi_write_speed(bus, hz); > > > > > > + /* to ensure spi_calibration is run when SCLK frequency change */ > > > + plat->max_hz = hz; > > > + > > > > This looks like a hack, doesn't this change just subvert the condition > > below to enforce the calibration ? > > Nope. I checked through debugger where plat->max_hz is initialized once > with the value from device tree. When you use sf probe to change > frequency, the value is not reflected to plat->max_hz. Hence the > calibration is not run when frequency change. That lead to the sf probe > fail when running at 80MHz or higher. Note the priv->qspi_calibrated_hz > is updated after calibration succeed. > > Thanks > Chin Liang Here are the useful info U-Boot 2015.10-rc2-06835-gf7d7156-dirty (Sep 01 2015 - 08:29:14 +0000) CPU: Altera SoCFPGA Platform FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0 BOOT: SD/MMC External Transceiver (1.8V) Watchdog enabled I2C: ready DRAM: 1 GiB MMC: SOCFPGA DWMMC: 0 Using default environment In: serial Out: serial Err: serial Model: Altera SOCFPGA Cyclone V SoC Development Kit Net: Error: ethernet at ff702000 address not set. No ethernet found. Hit any key to stop autoboot: 0 => sf probe 0 1000000 SF: Detected N25Q512 with page size 256 Bytes, erase size 4 KiB, total 64 MiB => md ff705010 1 ff705010: 0000000f .... => sf probe 0 10000000 SF: Detected N25Q512 with page size 256 Bytes, erase size 4 KiB, total 64 MiB => md ff705010 1 ff705010: 0000000f .... => sf probe 0 20000000 SF: Detected N25Q512 with page size 256 Bytes, erase size 4 KiB, total 64 MiB => md ff705010 1 ff705010: 0000000d .... => sf probe 0 50000000 SF: Detected N25Q512 with page size 256 Bytes, erase size 4 KiB, total 64 MiB => md ff705010 1 ff705010: 00000007 .... => sf probe 0 80000000 SF: Detected N25Q512 with page size 256 Bytes, erase size 4 KiB, total 64 MiB => md ff705010 1 ff705010: 00000007 .... => sf probe 0 100000000 SF: Detected N25Q512 with page size 256 Bytes, erase size 4 KiB, total 64 MiB => md ff705010 1 ff705010: 00000007 .... Thanks Chin Liang > > > > > > /* Calibration required for different SCLK speed or chip select */ > > > if (priv->qspi_calibrated_hz != plat->max_hz || > > > priv->qspi_calibrated_cs != spi_chip_select(bus)) { > > > > Best regards, > > Marek Vasut >