* [U-Boot] [PATCH 3/4] spi: cadence_qspi: Ensure check for max frequency in place
@ 2015-09-08 1:18 Chin Liang See
2015-09-08 12:21 ` Jagan Teki
0 siblings, 1 reply; 4+ messages in thread
From: Chin Liang See @ 2015-09-08 1:18 UTC (permalink / raw)
To: u-boot
Ensure the intended SCLK frequency not exceeding the maximum
frequency. If that happen, SCLK will set to maximum frequency.
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vikas Manocha <vikas.manocha@st.com>
Cc: Jagannadh Teki <jteki@openedev.com>
Cc: Pavel Machek <pavel@denx.de>
---
drivers/spi/cadence_qspi.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 8c0f7dd..f430b5d 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -127,6 +127,11 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz)
struct cadence_spi_priv *priv = dev_get_priv(bus);
int err;
+ if (hz > plat->max_hz) {
+ hz = plat->max_hz;
+ puts("SF: Default to maximum supported SCLK frequency\n");
+ }
+
/* Disable QSPI */
cadence_qspi_apb_controller_disable(priv->regbase);
--
1.7.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread* [U-Boot] [PATCH 3/4] spi: cadence_qspi: Ensure check for max frequency in place
2015-09-08 1:18 [U-Boot] [PATCH 3/4] spi: cadence_qspi: Ensure check for max frequency in place Chin Liang See
@ 2015-09-08 12:21 ` Jagan Teki
2015-09-10 4:59 ` Chin Liang See
0 siblings, 1 reply; 4+ messages in thread
From: Jagan Teki @ 2015-09-08 12:21 UTC (permalink / raw)
To: u-boot
On 8 September 2015 at 06:48, Chin Liang See <clsee@altera.com> wrote:
> Ensure the intended SCLK frequency not exceeding the maximum
> frequency. If that happen, SCLK will set to maximum frequency.
>
> Signed-off-by: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Dinh Nguyen <dinh.linux@gmail.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Vikas Manocha <vikas.manocha@st.com>
> Cc: Jagannadh Teki <jteki@openedev.com>
> Cc: Pavel Machek <pavel@denx.de>
> ---
> drivers/spi/cadence_qspi.c | 5 +++++
> 1 files changed, 5 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
> index 8c0f7dd..f430b5d 100644
> --- a/drivers/spi/cadence_qspi.c
> +++ b/drivers/spi/cadence_qspi.c
> @@ -127,6 +127,11 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz)
> struct cadence_spi_priv *priv = dev_get_priv(bus);
> int err;
>
> + if (hz > plat->max_hz) {
> + hz = plat->max_hz;
> + puts("SF: Default to maximum supported SCLK frequency\n");
This print mayn't require just assign plat->max_hz enough.
Reviewed-by: Jagan Teki <jteki@openedev.com>
> + }
> +
> /* Disable QSPI */
> cadence_qspi_apb_controller_disable(priv->regbase);
thanks!
--
Jagan | openedev.
^ permalink raw reply [flat|nested] 4+ messages in thread* [U-Boot] [PATCH 3/4] spi: cadence_qspi: Ensure check for max frequency in place
2015-09-08 12:21 ` Jagan Teki
@ 2015-09-10 4:59 ` Chin Liang See
0 siblings, 0 replies; 4+ messages in thread
From: Chin Liang See @ 2015-09-10 4:59 UTC (permalink / raw)
To: u-boot
Hi,
On Tue, 2015-09-08 at 17:51 +0530, Jagan Teki wrote:
> On 8 September 2015 at 06:48, Chin Liang See <clsee@altera.com> wrote:
> > Ensure the intended SCLK frequency not exceeding the maximum
> > frequency. If that happen, SCLK will set to maximum frequency.
> >
> > Signed-off-by: Chin Liang See <clsee@altera.com>
> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > Cc: Dinh Nguyen <dinh.linux@gmail.com>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Stefan Roese <sr@denx.de>
> > Cc: Vikas Manocha <vikas.manocha@st.com>
> > Cc: Jagannadh Teki <jteki@openedev.com>
> > Cc: Pavel Machek <pavel@denx.de>
> > ---
> > drivers/spi/cadence_qspi.c | 5 +++++
> > 1 files changed, 5 insertions(+), 0 deletions(-)
> >
> > diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
> > index 8c0f7dd..f430b5d 100644
> > --- a/drivers/spi/cadence_qspi.c
> > +++ b/drivers/spi/cadence_qspi.c
> > @@ -127,6 +127,11 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz)
> > struct cadence_spi_priv *priv = dev_get_priv(bus);
> > int err;
> >
> > + if (hz > plat->max_hz) {
> > + hz = plat->max_hz;
> > + puts("SF: Default to maximum supported SCLK frequency\n");
>
> This print mayn't require just assign plat->max_hz enough.
Sure, I can update that.
Thanks
Chin Liang
>
> Reviewed-by: Jagan Teki <jteki@openedev.com>
>
> > + }
> > +
> > /* Disable QSPI */
> > cadence_qspi_apb_controller_disable(priv->regbase);
>
> thanks!
^ permalink raw reply [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH 1/4] spi: cadence_qspi: Ensure spi_calibration is run when sclk change
@ 2015-09-03 13:41 Chin Liang See
2015-09-03 13:42 ` [U-Boot] [PATCH 3/4] spi: cadence_qspi: Ensure check for max frequency in place Chin Liang See
0 siblings, 1 reply; 4+ messages in thread
From: Chin Liang See @ 2015-09-03 13:41 UTC (permalink / raw)
To: u-boot
Ensuring spi_calibration is run when there is a change of sclk
frequency. This will ensure the qspi flash access works for high
sclk frequency
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vikas Manocha <vikas.manocha@st.com>
Cc: Jagannadh Teki <jteki@openedev.com>
Cc: Pavel Machek <pavel@denx.de>
---
drivers/spi/cadence_qspi.c | 8 ++++----
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 34a0f46..300934e 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -37,7 +37,7 @@ static int cadence_spi_write_speed(struct udevice *bus, uint hz)
}
/* Calibration sequence to determine the read data capture delay register */
-static int spi_calibration(struct udevice *bus)
+static int spi_calibration(struct udevice *bus, uint hz)
{
struct cadence_spi_platdata *plat = bus->platdata;
struct cadence_spi_priv *priv = dev_get_priv(bus);
@@ -64,7 +64,7 @@ static int spi_calibration(struct udevice *bus)
}
/* use back the intended clock and find low range */
- cadence_spi_write_speed(bus, plat->max_hz);
+ cadence_spi_write_speed(bus, hz);
for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
/* Disable QSPI */
cadence_qspi_apb_controller_disable(base);
@@ -111,7 +111,7 @@ static int spi_calibration(struct udevice *bus)
(range_hi + range_lo) / 2, range_lo, range_hi);
/* just to ensure we do once only when speed or chip select change */
- priv->qspi_calibrated_hz = plat->max_hz;
+ priv->qspi_calibrated_hz = hz;
priv->qspi_calibrated_cs = spi_chip_select(bus);
return 0;
@@ -131,7 +131,7 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz)
/* Calibration required for different SCLK speed or chip select */
if (priv->qspi_calibrated_hz != plat->max_hz ||
priv->qspi_calibrated_cs != spi_chip_select(bus)) {
- err = spi_calibration(bus);
+ err = spi_calibration(bus, hz);
if (err)
return err;
}
--
1.7.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread* [U-Boot] [PATCH 3/4] spi: cadence_qspi: Ensure check for max frequency in place
2015-09-03 13:41 [U-Boot] [PATCH 1/4] spi: cadence_qspi: Ensure spi_calibration is run when sclk change Chin Liang See
@ 2015-09-03 13:42 ` Chin Liang See
0 siblings, 0 replies; 4+ messages in thread
From: Chin Liang See @ 2015-09-03 13:42 UTC (permalink / raw)
To: u-boot
Ensure the intended SCLK frequency not exceeding the maximum
frequency. If that happen, SCLK will set to maximum frequency.
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vikas Manocha <vikas.manocha@st.com>
Cc: Jagannadh Teki <jteki@openedev.com>
Cc: Pavel Machek <pavel@denx.de>
---
drivers/spi/cadence_qspi.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index a00af87..52c29d5 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -123,6 +123,11 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz)
struct cadence_spi_priv *priv = dev_get_priv(bus);
int err;
+ if (hz > plat->max_hz) {
+ hz = plat->max_hz;
+ puts("SF: Default to maximum supported SCLK frequency\n");
+ }
+
/* Disable QSPI */
cadence_qspi_apb_controller_disable(priv->regbase);
--
1.7.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
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2015-09-08 1:18 [U-Boot] [PATCH 3/4] spi: cadence_qspi: Ensure check for max frequency in place Chin Liang See
2015-09-08 12:21 ` Jagan Teki
2015-09-10 4:59 ` Chin Liang See
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2015-09-03 13:41 [U-Boot] [PATCH 1/4] spi: cadence_qspi: Ensure spi_calibration is run when sclk change Chin Liang See
2015-09-03 13:42 ` [U-Boot] [PATCH 3/4] spi: cadence_qspi: Ensure check for max frequency in place Chin Liang See
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