[U-Boot] [Patch v2 04/16] net/fm: bug fix when CONFIG

public inbox for u-boot@lists.denx.de
 help / color / mirror / Atom feed

* [U-Boot] [Patch v2 04/16] net/fm: bug fix when CONFIG_PHYLIB not defined
@ 2015-09-17  7:06 Gong Qianyu
  2015-09-17  7:06 ` [U-Boot] [Patch v2 05/16] net: Move some header files to include/ Gong Qianyu
                   ` (11 more replies)
  0 siblings, 12 replies; 33+ messages in thread
From: Gong Qianyu @ 2015-09-17  7:06 UTC (permalink / raw)
  To: u-boot

From: Shaohui Xie <Shaohui.Xie@freescale.com>

phy_shutdown should be wrapped by CONFIG_PHYLIB.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
---
 drivers/net/fm/eth.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index cd05dbc..67c96a2 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -453,8 +453,10 @@ static void fm_eth_halt(struct eth_device *dev)
 	/* disable bmi Rx port */
 	bmi_rx_port_disable(fm_eth->rx_port);
 
+#ifdef CONFIG_PHYLIB
 	if (fm_eth->phydev)
 		phy_shutdown(fm_eth->phydev);
+#endif
 }
 
 static int fm_eth_send(struct eth_device *dev, void *buf, int len)
-- 
2.1.0.27.g96db324

^ permalink raw reply related	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 05/16] net: Move some header files to include/
  2015-09-17  7:06 [U-Boot] [Patch v2 04/16] net/fm: bug fix when CONFIG_PHYLIB not defined Gong Qianyu
@ 2015-09-17  7:06 ` Gong Qianyu
  2015-09-17 18:06   ` Scott Wood
  2015-09-17  7:06 ` [U-Boot] [Patch v2 06/16] net/fm: Add QSGMII PCS init Gong Qianyu
                   ` (10 subsequent siblings)
  11 siblings, 1 reply; 33+ messages in thread
From: Gong Qianyu @ 2015-09-17  7:06 UTC (permalink / raw)
  To: u-boot

From: Shaohui Xie <Shaohui.Xie@freescale.com>

The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM
and PPC, move it out of ppc to include/, and change the path in
drivers accordingly.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
---
 arch/powerpc/include/asm/fsl_dtsec.h        | 231 --------------
 arch/powerpc/include/asm/fsl_fman.h         | 463 ----------------------------
 arch/powerpc/include/asm/fsl_tgec.h         | 202 ------------
 arch/powerpc/include/asm/immap_85xx.h       |   2 +-
 board/freescale/b4860qds/eth_b4860qds.c     |   2 +-
 board/freescale/corenet_ds/eth_hydra.c      |   2 +-
 board/freescale/corenet_ds/eth_p4080.c      |   2 +-
 board/freescale/corenet_ds/eth_superhydra.c |   2 +-
 board/freescale/p1023rdb/p1023rdb.c         |   2 +-
 board/freescale/p2041rdb/eth.c              |   2 +-
 board/freescale/t102xqds/eth_t102xqds.c     |   2 +-
 board/freescale/t102xrdb/eth_t102xrdb.c     |   2 +-
 board/freescale/t1040qds/eth.c              |   2 +-
 board/freescale/t104xrdb/eth.c              |   2 +-
 board/freescale/t208xqds/eth_t208xqds.c     |   2 +-
 board/freescale/t208xrdb/eth_t208xrdb.c     |   2 +-
 board/freescale/t4qds/eth.c                 |   2 +-
 board/freescale/t4rdb/eth.c                 |   2 +-
 drivers/net/fm/dtsec.c                      |   2 +-
 drivers/net/fm/eth.c                        |  18 +-
 drivers/net/fm/fm.h                         |   2 +-
 drivers/net/fm/tgec.c                       |   2 +-
 drivers/net/fm/tgec_phy.c                   |   2 +-
 include/fsl_dtsec.h                         | 231 ++++++++++++++
 include/fsl_fman.h                          | 463 ++++++++++++++++++++++++++++
 include/fsl_tgec.h                          | 202 ++++++++++++
 26 files changed, 924 insertions(+), 924 deletions(-)

diff --git a/arch/powerpc/include/asm/fsl_dtsec.h b/arch/powerpc/include/asm/fsl_dtsec.h
deleted file mode 100644
index 41b8398..0000000
--- a/arch/powerpc/include/asm/fsl_dtsec.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __DTSEC_H__
-#define __DTSEC_H__
-
-#include <asm/types.h>
-
-struct dtsec {
-	u32	tsec_id;	/* controller ID and version */
-	u32	tsec_id2;	/* controller ID and configuration */
-	u32	ievent;		/* interrupt event */
-	u32	imask;		/* interrupt mask */
-	u32	res0;
-	u32	ecntrl;		/* ethernet control and configuration */
-	u32	ptv;		/* pause time value */
-	u32	tbipa;		/* TBI PHY address */
-	u32	res1[8];
-	u32	tctrl;		/* Transmit control register */
-	u32	res2[3];
-	u32	rctrl;		/* Receive control register */
-	u32	res3[11];
-	u32	igaddr[8];	/* Individual group address */
-	u32	gaddr[8];	/* group address */
-	u32	res4[16];
-	u32	maccfg1;	/* MAC configuration register 1 */
-	u32	maccfg2;	/* MAC configuration register 2 */
-	u32	ipgifg;		/* inter-packet/inter-frame gap */
-	u32	hafdup;		/* half-duplex control */
-	u32	maxfrm;		/* Maximum frame size */
-	u32	res5[3];
-	u32	miimcfg;	/* MII management configuration */
-	u32	miimcom;	/* MII management command */
-	u32	miimadd;	/* MII management address */
-	u32	miimcon;	/* MII management control */
-	u32	miimstat;	/* MII management status */
-	u32	miimind;	/* MII management indicator */
-	u32	res6;
-	u32	ifstat;		/* Interface status */
-	u32	macstnaddr1;	/* MAC station address 1 */
-	u32	macstnaddr2;	/* MAC station address 2 */
-	u32	res7[46];
-	/* transmit and receive counter */
-	u32	tr64;		/* Tx and Rx 64 bytes frame */
-	u32	tr127;		/* Tx and Rx 65 to 127 bytes frame */
-	u32	tr255;		/* Tx and Rx 128 to 255 bytes frame */
-	u32	tr511;		/* Tx and Rx 256 to 511 bytes frame */
-	u32	tr1k;		/* Tx and Rx 512 to 1023 bytes frame */
-	u32	trmax;		/* Tx and Rx 1024 to 1518 bytes frame */
-	u32	trmgv;		/* Tx and Rx 1519 to 1522 good VLAN frame */
-	/* receive counters */
-	u32	rbyt;		/* Receive byte counter */
-	u32	rpkt;		/* Receive packet counter */
-	u32	rfcs;		/* Receive FCS error */
-	u32	rmca;		/* Receive multicast packet */
-	u32	rbca;		/* Receive broadcast packet */
-	u32	rxcf;		/* Receive control frame */
-	u32	rxpf;		/* Receive pause frame */
-	u32	rxuo;		/* Receive unknown OP code */
-	u32	raln;		/* Receive alignment error */
-	u32	rflr;		/* Receive frame length error */
-	u32	rcde;		/* Receive code error */
-	u32	rcse;		/* Receive carrier sense error */
-	u32	rund;		/* Receive undersize packet */
-	u32	rovr;		/* Receive oversize packet */
-	u32	rfrg;		/* Receive fragments counter */
-	u32	rjbr;		/* Receive jabber counter */
-	u32	rdrp;		/* Receive drop counter */
-	/* transmit counters */
-	u32	tbyt;		/* Transmit byte counter */
-	u32	tpkt;		/* Transmit packet */
-	u32	tmca;		/* Transmit multicast packet */
-	u32	tbca;		/* Transmit broadcast packet */
-	u32	txpf;		/* Transmit pause control frame */
-	u32	tdfr;		/* Transmit deferral packet */
-	u32	tedf;		/* Transmit excessive deferral pkt */
-	u32	tscl;		/* Transmit single collision pkt */
-	u32	tmcl;		/* Transmit multiple collision pkt */
-	u32	tlcl;		/* Transmit late collision pkt */
-	u32	txcl;		/* Transmit excessive collision */
-	u32	tncl;		/* Transmit total collision */
-	u32	res8;
-	u32	tdrp;		/* Transmit drop frame */
-	u32	tjbr;		/* Transmit jabber frame */
-	u32	tfcs;		/* Transmit FCS error */
-	u32	txcf;		/* Transmit control frame */
-	u32	tovr;		/* Transmit oversize frame */
-	u32	tund;		/* Transmit undersize frame */
-	u32	tfrg;		/* Transmit fragments frame */
-	/* counter controls */
-	u32	car1;		/* carry register 1 */
-	u32	car2;		/* carry register 2 */
-	u32	cam1;		/* carry register 1 mask */
-	u32	cam2;		/* carry register 2 mask */
-	u32	res9[80];
-};
-
-
-/* TBI register addresses */
-#define TBI_CR			0x00
-#define TBI_SR			0x01
-#define TBI_ANA			0x04
-#define TBI_ANLPBPA		0x05
-#define TBI_ANEX		0x06
-#define TBI_TBICON		0x11
-
-/* TBI MDIO register bit fields*/
-#define TBICON_CLK_SELECT	0x0020
-#define TBIANA_ASYMMETRIC_PAUSE 0x0100
-#define TBIANA_SYMMETRIC_PAUSE  0x0080
-#define TBIANA_HALF_DUPLEX	0x0040
-#define TBIANA_FULL_DUPLEX	0x0020
-#define TBICR_PHY_RESET		0x8000
-#define TBICR_ANEG_ENABLE	0x1000
-#define TBICR_RESTART_ANEG	0x0200
-#define TBICR_FULL_DUPLEX	0x0100
-#define TBICR_SPEED1_SET	0x0040
-
-/* IEVENT - interrupt events register */
-#define IEVENT_BABR	0x80000000 /* Babbling receive error */
-#define IEVENT_RXC	0x40000000 /* pause control frame received */
-#define IEVENT_MSRO	0x04000000 /* MIB counter overflow */
-#define IEVENT_GTSC	0x02000000 /* Graceful transmit stop complete */
-#define IEVENT_BABT	0x01000000 /* Babbling transmit error */
-#define IEVENT_TXC	0x00800000 /* control frame transmitted */
-#define IEVENT_TXE	0x00400000 /* Transmit channel error */
-#define IEVENT_LC	0x00040000 /* Late collision occurred */
-#define IEVENT_CRL	0x00020000 /* Collision retry exceed limit */
-#define IEVENT_XFUN	0x00010000 /* Transmit FIFO underrun */
-#define IEVENT_ABRT	0x00008000 /* Transmit packet abort */
-#define IEVENT_MMRD	0x00000400 /* MII management read complete */
-#define IEVENT_MMWR	0x00000200 /* MII management write complete */
-#define IEVENT_GRSC	0x00000100 /* Graceful stop complete */
-#define IEVENT_TDPE	0x00000002 /* Internal data parity error on Tx */
-#define IEVENT_RDPE	0x00000001 /* Internal data parity error on Rx */
-
-#define IEVENT_CLEAR_ALL	0xffffffff
-
-/* IMASK - interrupt mask register */
-#define IMASK_BREN	0x80000000 /* Babbling receive enable */
-#define IMASK_RXCEN	0x40000000 /* receive control enable */
-#define IMASK_MSROEN	0x04000000 /* MIB counter overflow enable */
-#define IMASK_GTSCEN	0x02000000 /* Graceful Tx stop complete enable */
-#define IMASK_BTEN	0x01000000 /* Babbling transmit error enable */
-#define IMASK_TXCEN	0x00800000 /* control frame transmitted enable */
-#define IMASK_TXEEN	0x00400000 /* Transmit channel error enable */
-#define IMASK_LCEN	0x00040000 /* Late collision interrupt enable */
-#define IMASK_CRLEN	0x00020000 /* Collision retry exceed limit */
-#define IMASK_XFUNEN	0x00010000 /* Transmit FIFO underrun enable */
-#define IMASK_ABRTEN	0x00008000 /* Transmit packet abort enable */
-#define IMASK_MMRDEN	0x00000400 /* MII management read complete enable */
-#define IMASK_MMWREN	0x00000200 /* MII management write complete enable */
-#define IMASK_GRSCEN	0x00000100 /* Graceful stop complete interrupt enable */
-#define IMASK_TDPEEN	0x00000002 /* Internal data parity error on Tx enable */
-#define IMASK_RDPEEN	0x00000001 /* Internal data parity error on Rx enable */
-
-#define IMASK_MASK_ALL	0x00000000
-
-/* ECNTRL - ethernet control register */
-#define ECNTRL_CFG_RO	0x80000000 /* GMIIM, RPM, R100M, SGMIIM bits are RO */
-#define ECNTRL_CLRCNT	0x00004000 /* clear all statistics */
-#define ECNTRL_AUTOZ	0x00002000 /* auto zero MIB counter */
-#define ECNTRL_STEN	0x00001000 /* enable internal counters to update */
-#define ECNTRL_GMIIM	0x00000040 /* 1- GMII or RGMII interface mode */
-#define ECNTRL_TBIM	0x00000020 /* 1- Ten-bit interface mode */
-#define ECNTRL_RPM	0x00000010 /* 1- RGMII reduced-pin mode */
-#define ECNTRL_R100M	0x00000008 /* 1- RGMII 100 Mbps, SGMII 100 Mbps
-				      0- RGMII 10 Mbps, SGMII 10 Mbps */
-#define ECNTRL_SGMIIM	0x00000002 /* 1- SGMII interface mode */
-#define ECNTRL_TBIM	0x00000020 /* 1- TBI Interface mode (for SGMII) */
-
-#define ECNTRL_DEFAULT	(ECNTRL_TBIM | ECNTRL_R100M | ECNTRL_SGMIIM)
-
-/* TCTRL - Transmit control register */
-#define TCTRL_THDF	0x00000800 /* Transmit half-duplex flow control */
-#define TCTRL_TTSE	0x00000040 /* Transmit time-stamp enable */
-#define TCTRL_GTS	0x00000020 /* Graceful transmit stop */
-#define TCTRL_RFC_PAUSE	0x00000010 /* Receive flow control pause frame */
-
-/* RCTRL - Receive control register */
-#define RCTRL_PAL_MASK	0x001f0000 /* packet alignment padding length */
-#define RCTRL_PAL_SHIFT	16
-#define RCTRL_CFA	0x00008000 /* control frame accept enable */
-#define RCTRL_GHTX	0x00000800 /* group address hash table extend */
-#define RCTRL_RTSE	0x00000040 /* receive 1588 time-stamp enable */
-#define RCTRL_GRS	0x00000020 /* graceful receive stop */
-#define RCTRL_BC_REJ	0x00000010 /* broadcast frame reject */
-#define RCTRL_BC_MPROM	0x00000008 /* all multicast/broadcast frames received */
-#define RCTRL_RSF	0x00000004 /* receive short frame(17~63 bytes) enable */
-#define RCTRL_EMEN	0x00000002 /* Exact match MAC address enable */
-#define RCTRL_UPROM	0x00000001 /* all unicast frame received */
-
-/* MACCFG1 - MAC configuration 1 register */
-#define MACCFG1_SOFT_RST	0x80000000 /* place the MAC in reset */
-#define MACCFG1_RST_RXMAC	0x00080000 /* reset receive MAC control block */
-#define MACCFG1_RST_TXMAC	0x00040000 /* reet transmit MAC control block */
-#define MACCFG1_RST_RXFUN	0x00020000 /* reset receive function block */
-#define MACCFG1_RST_TXFUN	0x00010000 /* reset transmit function block */
-#define MACCFG1_LOOPBACK	0x00000100 /* MAC loopback */
-#define MACCFG1_RX_FLOW		0x00000020 /* Receive flow */
-#define MACCFG1_TX_FLOW		0x00000010 /* Transmit flow */
-#define MACCFG1_SYNC_RXEN	0x00000008 /* Frame reception enabled */
-#define MACCFG1_RX_EN		0x00000004 /* Rx enable */
-#define MACCFG1_SYNC_TXEN	0x00000002 /* Frame transmission is enabled */
-#define MACCFG1_TX_EN		0x00000001 /* Tx enable */
-#define MACCFG1_RXTX_EN		(MACCFG1_RX_EN | MACCFG1_TX_EN)
-
-/* MACCFG2 - MAC configuration 2 register */
-#define MACCFG2_PRE_LEN_MASK	0x0000f000 /* preamble length */
-#define MACCFG2_PRE_LEN(x)	((x << 12) & MACCFG2_PRE_LEN_MASK)
-#define MACCFG2_IF_MODE_MASK	0x00000300
-#define MACCFG2_IF_MODE_NIBBLE	0x00000100 /* MII, 10/100 Mbps MII/RMII */
-#define MACCFG2_IF_MODE_BYTE	0x00000200 /* GMII/TBI, 1000 GMII/TBI */
-#define MACCFG2_PRE_RX_EN	0x00000080 /* receive preamble enable */
-#define MACCFG2_PRE_TX_EN	0x00000040 /* tx preable enable */
-#define MACCFG2_HUGE_FRAME	0x00000020 /* >= max frame len enable */
-#define MACCFG2_LEN_CHECK	0x00000010 /* MAC check frame's length Rx */
-#define MACCFG2_MAG_EN		0x00000008 /* magic packet enable */
-#define MACCFG2_PAD_CRC		0x00000004 /* pad and append CRC */
-#define MACCFG2_CRC_EN		0x00000002 /* MAC appends a CRC on all frames */
-#define MACCFG2_FULL_DUPLEX	0x00000001 /* Full deplex mode */
-
-struct fsl_enet_mac;
-
-void init_dtsec(struct fsl_enet_mac *mac, void *base, void *phyregs,
-		int max_rx_len);
-
-#endif
diff --git a/arch/powerpc/include/asm/fsl_fman.h b/arch/powerpc/include/asm/fsl_fman.h
deleted file mode 100644
index 4d04415..0000000
--- a/arch/powerpc/include/asm/fsl_fman.h
+++ /dev/null
@@ -1,463 +0,0 @@
-/*
- * MPC85xx Internal Memory Map
- *
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __FSL_FMAN_H__
-#define __FSL_FMAN_H__
-
-#include <asm/types.h>
-
-typedef struct fm_bmi_common {
-	u32	fmbm_init;	/* BMI initialization */
-	u32	fmbm_cfg1;	/* BMI configuration1 */
-	u32	fmbm_cfg2;	/* BMI configuration2 */
-	u32	res0[0x5];
-	u32	fmbm_ievr;	/* interrupt event register */
-	u32	fmbm_ier;	/* interrupt enable register */
-	u32	fmbm_ifr;	/* interrupt force register */
-	u32	res1[0x5];
-	u32	fmbm_arb[0x8];	/* BMI arbitration */
-	u32	res2[0x28];
-	u32	fmbm_gde;	/* global debug enable */
-	u32	fmbm_pp[0x3f];	/* BMI port parameters */
-	u32	res3;
-	u32	fmbm_pfs[0x3f];	/* BMI port FIFO size */
-	u32	res4;
-	u32	fmbm_ppid[0x3f];/* port partition ID */
-} fm_bmi_common_t;
-
-typedef struct fm_qmi_common {
-	u32	fmqm_gc;	/* general configuration register */
-	u32	res0;
-	u32	fmqm_eie;	/* error interrupt event register */
-	u32	fmqm_eien;	/* error interrupt enable register */
-	u32	fmqm_eif;	/* error interrupt force register */
-	u32	fmqm_ie;	/* interrupt event register */
-	u32	fmqm_ien;	/* interrupt enable register */
-	u32	fmqm_if;	/* interrupt force register */
-	u32	fmqm_gs;	/* global status register */
-	u32	fmqm_ts;	/* task status register */
-	u32	fmqm_etfc;	/* enqueue total frame counter */
-	u32	fmqm_dtfc;	/* dequeue total frame counter */
-	u32	fmqm_dc0;	/* dequeue counter 0 */
-	u32	fmqm_dc1;	/* dequeue counter 1 */
-	u32	fmqm_dc2;	/* dequeue counter 2 */
-	u32	fmqm_dc3;	/* dequeue counter 3 */
-	u32	fmqm_dfnoc;	/* dequeue FQID not override counter */
-	u32	fmqm_dfcc;	/* dequeue FQID from context counter */
-	u32	fmqm_dffc;	/* dequeue FQID from FD counter */
-	u32	fmqm_dcc;	/* dequeue confirm counter */
-	u32	res1[0xc];
-	u32	fmqm_dtrc;	/* debug trap configuration register */
-	u32	fmqm_efddd;	/* enqueue frame descriptor dynamic debug */
-	u32	res3[0x2];
-	u32	res4[0xdc];	/* missing debug regs */
-} fm_qmi_common_t;
-
-typedef struct fm_bmi {
-	u8	res[1024];
-} fm_bmi_t;
-
-typedef struct fm_qmi {
-	u8	res[1024];
-} fm_qmi_t;
-
-struct fm_bmi_rx_port {
-	u32 fmbm_rcfg;	/* Rx configuration */
-	u32 fmbm_rst;	/* Rx status */
-	u32 fmbm_rda;	/* Rx DMA attributes */
-	u32 fmbm_rfp;	/* Rx FIFO parameters */
-	u32 fmbm_rfed;	/* Rx frame end data */
-	u32 fmbm_ricp;	/* Rx internal context parameters */
-	u32 fmbm_rim;	/* Rx internal margins */
-	u32 fmbm_rebm;	/* Rx external buffer margins */
-	u32 fmbm_rfne;	/* Rx frame next engine */
-	u32 fmbm_rfca;	/* Rx frame command attributes */
-	u32 fmbm_rfpne;	/* Rx frame parser next engine */
-	u32 fmbm_rpso;	/* Rx parse start offset */
-	u32 fmbm_rpp;	/* Rx policer profile */
-	u32 fmbm_rccb;	/* Rx coarse classification base */
-	u32 res1[0x2];
-	u32 fmbm_rprai[0x8];	/* Rx parse results array Initialization */
-	u32 fmbm_rfqid;		/* Rx frame queue ID */
-	u32 fmbm_refqid;	/* Rx error frame queue ID */
-	u32 fmbm_rfsdm;		/* Rx frame status discard mask */
-	u32 fmbm_rfsem;		/* Rx frame status error mask */
-	u32 fmbm_rfene;		/* Rx frame enqueue next engine */
-	u32 res2[0x23];
-	u32 fmbm_ebmpi[0x8];	/* buffer manager pool information */
-	u32 fmbm_acnt[0x8];	/* allocate counter */
-	u32 res3[0x8];
-	u32 fmbm_cgm[0x8];	/* congestion group map */
-	u32 fmbm_mpd;		/* BMan pool depletion */
-	u32 res4[0x1F];
-	u32 fmbm_rstc;		/* Rx statistics counters */
-	u32 fmbm_rfrc;		/* Rx frame counters */
-	u32 fmbm_rfbc;		/* Rx bad frames counter */
-	u32 fmbm_rlfc;		/* Rx large frames counter */
-	u32 fmbm_rffc;		/* Rx filter frames counter */
-	u32 fmbm_rfdc;		/* Rx frame discard counter */
-	u32 fmbm_rfldec;	/* Rx frames list DMA error counter */
-	u32 fmbm_rodc;		/* Rx out of buffers discard counter */
-	u32 fmbm_rbdc;		/* Rx buffers deallocate counter */
-	u32 res5[0x17];
-	u32 fmbm_rpc;		/* Rx performance counters */
-	u32 fmbm_rpcp;		/* Rx performance count parameters */
-	u32 fmbm_rccn;		/* Rx cycle counter */
-	u32 fmbm_rtuc;		/* Rx tasks utilization counter */
-	u32 fmbm_rrquc;		/* Rx receive queue utilization counter */
-	u32 fmbm_rduc;		/* Rx DMA utilization counter */
-	u32 fmbm_rfuc;		/* Rx FIFO utilization counter */
-	u32 fmbm_rpac;		/* Rx pause activation counter */
-	u32 res6[0x18];
-	u32 fmbm_rdbg;		/* Rx debug configuration */
-};
-
-/* FMBM_RCFG - Rx configuration */
-#define FMBM_RCFG_EN		0x80000000 /* port is enabled to receive data */
-#define FMBM_RCFG_FDOVR		0x02000000 /* frame discard override */
-#define FMBM_RCFG_IM		0x01000000 /* independent mode */
-
-/* FMBM_RST - Rx status */
-#define FMBM_RST_BSY		0x80000000 /* Rx port is busy */
-
-/* FMBM_RFCA - Rx frame command attributes */
-#define FMBM_RFCA_ORDER		0x80000000
-#define FMBM_RFCA_MR_MASK	0x003f0000
-#define FMBM_RFCA_MR(x)		((x << 16) & FMBM_RFCA_MR_MASK)
-
-/* FMBM_RSTC - Rx statistics */
-#define FMBM_RSTC_EN		0x80000000 /* statistics counters enable */
-
-struct fm_bmi_tx_port {
-	u32 fmbm_tcfg;	/* Tx configuration */
-	u32 fmbm_tst;	/* Tx status */
-	u32 fmbm_tda;	/* Tx DMA attributes */
-	u32 fmbm_tfp;	/* Tx FIFO parameters */
-	u32 fmbm_tfed;	/* Tx frame end data */
-	u32 fmbm_ticp;	/* Tx internal context parameters */
-	u32 fmbm_tfne;	/* Tx frame next engine */
-	u32 fmbm_tfca;	/* Tx frame command attributes */
-	u32 fmbm_tcfqid;/* Tx confirmation frame queue ID */
-	u32 fmbm_tfeqid;/* Tx error frame queue ID */
-	u32 fmbm_tfene;	/* Tx frame enqueue next engine */
-	u32 fmbm_trlmts;/* Tx rate limiter scale */
-	u32 fmbm_trlmt;	/* Tx rate limiter */
-	u32 res0[0x73];
-	u32 fmbm_tstc;	/* Tx statistics counters */
-	u32 fmbm_tfrc;	/* Tx frame counter */
-	u32 fmbm_tfdc;	/* Tx frames discard counter */
-	u32 fmbm_tfledc;/* Tx frame length error discard counter */
-	u32 fmbm_tfufdc;/* Tx frame unsupported format discard counter */
-	u32 fmbm_tbdc;	/* Tx buffers deallocate counter */
-	u32 res1[0x1a];
-	u32 fmbm_tpc;	/* Tx performance counters */
-	u32 fmbm_tpcp;	/* Tx performance count parameters */
-	u32 fmbm_tccn;	/* Tx cycle counter */
-	u32 fmbm_ttuc;	/* Tx tasks utilization counter */
-	u32 fmbm_ttcquc;/* Tx transmit confirm queue utilization counter */
-	u32 fmbm_tduc;	/* Tx DMA utilization counter */
-	u32 fmbm_tfuc;	/* Tx FIFO utilization counter */
-	u32 res2[0x19];
-	u32 fmbm_tdcfg;	/* Tx debug configuration */
-};
-
-/* FMBM_TCFG - Tx configuration */
-#define FMBM_TCFG_EN	0x80000000 /* port is enabled to transmit data */
-#define FMBM_TCFG_IM	0x01000000 /* independent mode enable */
-
-/* FMBM_TST - Tx status */
-#define FMBM_TST_BSY		0x80000000 /* Tx port is busy */
-
-/* FMBM_TFCA - Tx frame command attributes */
-#define FMBM_TFCA_ORDER		0x80000000
-#define FMBM_TFCA_MR_MASK	0x003f0000
-#define FMBM_TFCA_MR(x)		((x << 16) & FMBM_TFCA_MR_MASK)
-
-/* FMBM_TSTC - Tx statistics counters */
-#define FMBM_TSTC_EN		0x80000000
-
-/* FMBM_INIT - BMI initialization register */
-#define FMBM_INIT_START		0x80000000 /* init internal buffers */
-
-/* FMBM_CFG1 - BMI configuration 1 */
-#define FMBM_CFG1_FBPS_MASK	0x03ff0000 /* Free buffer pool size */
-#define FMBM_CFG1_FBPS_SHIFT	16
-#define FMBM_CFG1_FBPO_MASK	0x000003ff /* Free buffer pool offset */
-
-/* FMBM_IEVR - interrupt event */
-#define FMBM_IEVR_PEC		0x80000000 /* pipeline table ECC err detected */
-#define FMBM_IEVR_LEC		0x40000000 /* linked list RAM ECC error */
-#define FMBM_IEVR_SEC		0x20000000 /* statistics count RAM ECC error */
-#define FMBM_IEVR_CLEAR_ALL	(FMBM_IEVR_PEC | FMBM_IEVR_LEC | FMBM_IEVR_SEC)
-
-/* FMBM_IER - interrupt enable */
-#define FMBM_IER_PECE		0x80000000 /* PEC interrupt enable */
-#define FMBM_IER_LECE		0x40000000 /* LEC interrupt enable */
-#define FMBM_IER_SECE		0x20000000 /* SEC interrupt enable */
-
-#define FMBM_IER_DISABLE_ALL	0x00000000
-
-/* FMBM_PP - BMI Port Parameters */
-#define FMBM_PP_MXT_MASK	0x3f000000 /* Max # tasks */
-#define FMBM_PP_MXT(x)		(((x-1) << 24) & FMBM_PP_MXT_MASK)
-#define FMBM_PP_MXD_MASK	0x00000f00 /* Max DMA */
-#define FMBM_PP_MXD(x)		(((x-1) << 8) & FMBM_PP_MXD_MASK)
-
-/* FMBM_PFS - BMI Port FIFO Size */
-#define FMBM_PFS_IFSZ_MASK	0x000003ff /* Internal Fifo Size */
-#define FMBM_PFS_IFSZ(x)	(x & FMBM_PFS_IFSZ_MASK)
-
-/* FMQM_GC - global configuration */
-#define FMQM_GC_ENQ_EN		0x80000000 /* enqueue enable */
-#define FMQM_GC_DEQ_EN		0x40000000 /* dequeue enable */
-#define FMQM_GC_STEN		0x10000000 /* enable global stat counters */
-#define FMQM_GC_ENQ_THR_MASK	0x00003f00 /* max number of enqueue Tnum */
-#define FMQM_GC_ENQ(x)		((x << 8) &  FMQM_GC_ENQ_THR_MAS)
-#define FMQM_GC_DEQ_THR_MASK	0x0000003f /* max number of dequeue Tnum */
-#define FMQM_GC_DEQ(x)		(x & FMQM_GC_DEQ_THR_MASK)
-
-/* FMQM_EIE - error interrupt event register */
-#define FMQM_EIE_DEE		0x80000000 /* double-bit ECC error */
-#define FMQM_EIE_DFUPE		0x40000000 /* dequeue from unknown PortID */
-#define FMQM_EIE_CLEAR_ALL	(FMQM_EIE_DEE | FMQM_EIE_DFUPE)
-
-/* FMQM_EIEN - error interrupt enable register */
-#define FMQM_EIEN_DEEN		0x80000000 /* double-bit ECC error */
-#define FMQM_EIEN_DFUPEN	0x40000000 /* dequeue from unknown PortID */
-#define FMQM_EIEN_DISABLE_ALL	0x00000000
-
-/* FMQM_IE - interrupt event register */
-#define FMQM_IE_SEE		0x80000000 /* single-bit ECC error detected */
-#define FMQM_IE_CLEAR_ALL	FMQM_IE_SEE
-
-/* FMQM_IEN - interrupt enable register */
-#define FMQM_IEN_SEE		0x80000000 /* single-bit ECC err IRQ enable */
-#define FMQM_IEN_DISABLE_ALL	0x00000000
-
-/* NIA - next invoked action */
-#define NIA_ENG_RISC		0x00000000
-#define NIA_ENG_MASK		0x007c0000
-
-/* action code */
-#define NIA_RISC_AC_CC		0x00000006
-#define NIA_RISC_AC_IM_TX	0x00000008 /* independent mode Tx */
-#define NIA_RISC_AC_IM_RX	0x0000000a /* independent mode Rx */
-#define NIA_RISC_AC_HC		0x0000000c
-
-typedef struct fm_parser {
-	u8	res[1024];
-} fm_parser_t;
-
-typedef struct fm_policer {
-	u8	res[4*1024];
-} fm_policer_t;
-
-typedef struct fm_keygen {
-	u8	res[4*1024];
-} fm_keygen_t;
-
-typedef struct fm_dma {
-	u32	fmdmsr;		/* status register */
-	u32	fmdmmr;		/* mode register */
-	u32	fmdmtr;		/* bus threshold register */
-	u32	fmdmhy;		/* bus hysteresis register */
-	u32	fmdmsetr;	/* SOS emergency threshold register */
-	u32	fmdmtah;	/* transfer bus address high register */
-	u32	fmdmtal;	/* transfer bus address low register */
-	u32	fmdmtcid;	/* transfer bus communication ID register */
-	u32	fmdmra;		/* DMA bus internal ram address register */
-	u32	fmdmrd;		/* DMA bus internal ram data register */
-	u32	res0[0xb];
-	u32	fmdmdcr;	/* debug counter */
-	u32	fmdmemsr;	/* emrgency smoother register */
-	u32	res1;
-	u32	fmdmplr[32];	/* FM DMA PID-LIODN # register */
-	u32	res[0x3c8];
-} fm_dma_t;
-
-/* FMDMSR - Fman DMA status register */
-#define FMDMSR_CMDQNE		0x10000000 /* command queue not empty */
-#define FMDMSR_BER		0x08000000 /* bus err event occurred on bus */
-#define FMDMSR_RDB_ECC		0x04000000 /* read buffer ECC error */
-#define FMDMSR_WRB_SECC		0x02000000 /* write buf ECC err sys side */
-#define FMDMSR_WRB_FECC		0x01000000 /* write buf ECC err Fman side */
-#define FMDMSR_DPEXT_SECC	0x00800000 /* DP external ECC err sys side */
-#define FMDMSR_DPEXT_FECC	0x00400000 /* DP external ECC err Fman side */
-#define FMDMSR_DPDAT_SECC	0x00200000 /* DP data ECC err on sys side */
-#define FMDMSR_DPDAT_FECC	0x00100000 /* DP data ECC err on Fman side */
-#define FMDMSR_SPDAT_FECC	0x00080000 /* SP data ECC error Fman side */
-
-#define FMDMSR_CLEAR_ALL	(FMDMSR_BER | FMDMSR_RDB_ECC \
-				| FMDMSR_WRB_SECC | FMDMSR_WRB_FECC \
-				| FMDMSR_DPEXT_SECC | FMDMSR_DPEXT_FECC \
-				| FMDMSR_DPDAT_SECC | FMDMSR_DPDAT_FECC \
-				| FMDMSR_SPDAT_FECC)
-
-/* FMDMMR - FMan DMA mode register */
-#define FMDMMR_SBER		0x10000000 /* stop the DMA if a bus error */
-
-typedef struct fm_fpm {
-	u32	fpmtnc;		/* TNUM control */
-	u32	fpmprc;		/* Port_ID control */
-	u32	res0;
-	u32	fpmflc;		/* flush control */
-	u32	fpmdis1;	/* dispatch thresholds1 */
-	u32	fpmdis2;	/* dispatch thresholds2 */
-	u32	fmepi;		/* error pending interrupts */
-	u32	fmrie;		/* rams interrupt enable */
-	u32	fpmfcevent[0x4];/* FMan controller event 0-3 */
-	u32	res1[0x4];
-	u32	fpmfcmask[0x4];	/* FMan controller mask 0-3 */
-	u32	res2[0x4];
-	u32	fpmtsc1;	/* timestamp control1 */
-	u32	fpmtsc2;	/* timestamp control2 */
-	u32	fpmtsp;		/* time stamp */
-	u32	fpmtsf;		/* time stamp fraction */
-	u32	fpmrcr;		/* rams control and event */
-	u32	res3[0x3];
-	u32	fpmdrd[0x4];	/* data_ram data 0-3 */
-	u32	res4[0xc];
-	u32	fpmdra;		/* data ram access */
-	u32	fm_ip_rev_1;	/* IP block revision 1 */
-	u32	fm_ip_rev_2;	/* IP block revision 2 */
-	u32	fmrstc;		/* reset command */
-	u32	fmcld;		/* classifier debug control */
-	u32	fmnpi;		/* normal pending interrupts */
-	u32	res5;
-	u32	fmfpee;		/* event and enable */
-	u32	fpmcev[0x4];	/* CPU event 0-3 */
-	u32	res6[0x4];
-	u32	fmfp_ps[0x40];	/* port status */
-	u32	res7[0x260];
-	u32	fpmts[0x80];	/* task status */
-	u32	res8[0xa0];
-} fm_fpm_t;
-
-/* FMFP_PRC - FPM Port_ID Control Register */
-#define FMFPPRC_PORTID_MASK	0x3f000000
-#define FMFPPRC_PORTID_SHIFT	24
-#define FMFPPRC_ORA_SHIFT	16
-#define FMFPPRC_RISC1		0x00000001
-#define FMFPPRC_RISC2		0x00000002
-#define FMFPPRC_RISC_ALL	(FMFPPRC_RISC1 | FMFPPRC_RSIC2)
-
-/* FPM Flush Control Register */
-#define FMFP_FLC_DISP_LIM_NONE	0x00000000 /* no dispatch limitation */
-
-/* FMFP_EE - FPM event and enable register */
-#define FMFPEE_DECC		0x80000000 /* double ECC err on FPM ram */
-#define FMFPEE_STL		0x40000000 /* stall of task ... */
-#define FMFPEE_SECC		0x20000000 /* single ECC error */
-#define FMFPEE_RFM		0x00010000 /* release FMan */
-#define FMFPEE_DECC_EN		0x00008000 /* double ECC interrupt enable */
-#define FMFPEE_STL_EN		0x00004000 /* stall of task interrupt enable */
-#define FMFPEE_SECC_EN		0x00002000 /* single ECC err interrupt enable */
-#define FMFPEE_EHM		0x00000008 /* external halt enable */
-#define FMFPEE_UEC		0x00000004 /* FMan is not halted */
-#define FMFPEE_CER		0x00000002 /* only errornous task stalled */
-#define FMFPEE_DER		0x00000001 /* DMA error is just reported */
-
-#define FMFPEE_CLEAR_EVENT	(FMFPEE_DECC | FMFPEE_STL | FMFPEE_SECC | \
-				 FMFPEE_EHM | FMFPEE_UEC | FMFPEE_CER | \
-				 FMFPEE_DER | FMFPEE_RFM)
-
-/* FMFP_RCR - FMan Rams Control and Event */
-#define FMFP_RCR_MDEC		0x00008000 /* double ECC error in muram */
-#define FMFP_RCR_IDEC		0x00004000 /* double ECC error in iram */
-
-typedef struct fm_imem {
-	u32	iadd;		/* instruction address register */
-	u32	idata;		/* instruction data register */
-	u32	itcfg;		/* timing config register */
-	u32	iready;		/* ready register */
-	u8	res[0xff0];
-} fm_imem_t;
-#define IRAM_IADD_AIE		0x80000000 /* address auto increase enable */
-#define IRAM_READY		0x80000000 /* ready to use */
-
-typedef struct fm_soft_parser {
-	u8	res[4*1024];
-} fm_soft_parser_t;
-
-typedef struct fm_dtesc {
-	u8	res[4*1024];
-} fm_dtsec_t;
-
-typedef struct fm_mdio {
-	u8	res0[0x120];
-	u32	miimcfg;	/* MII management configuration reg */
-	u32	miimcom;	/* MII management command reg */
-	u32	miimadd;	/* MII management address reg */
-	u32	miimcon;	/* MII management control reg */
-	u32	miimstat;	/* MII management status reg  */
-	u32	miimind;	/* MII management indication reg */
-	u8	res1[0x1000 - 0x138];
-} fm_mdio_t;
-
-typedef struct fm_10gec {
-	u8	res[4*1024];
-} fm_10gec_t;
-
-typedef struct fm_10gec_mdio {
-	u8	res[4*1024];
-} fm_10gec_mdio_t;
-
-typedef struct fm_memac {
-	u8	res[4*1024];
-} fm_memac_t;
-
-typedef struct fm_memac_mdio {
-	u8	res[4*1024];
-} fm_memac_mdio_t;
-
-typedef struct fm_1588 {
-	u8	res[4*1024];
-} fm_1588_t;
-
-typedef struct ccsr_fman {
-	u8			muram[0x80000];
-	fm_bmi_common_t		fm_bmi_common;
-	fm_qmi_common_t		fm_qmi_common;
-	u8			res0[2048];
-	struct {
-		fm_bmi_t	fm_bmi;
-		fm_qmi_t	fm_qmi;
-		fm_parser_t	fm_parser;
-		u8		res[1024];
-	} port[63];
-	fm_policer_t		fm_policer;
-	fm_keygen_t		fm_keygen;
-	fm_dma_t		fm_dma;
-	fm_fpm_t		fm_fpm;
-	fm_imem_t		fm_imem;
-	u8			res1[8*1024];
-	fm_soft_parser_t	fm_soft_parser;
-	u8			res2[96*1024];
-#ifdef CONFIG_SYS_FMAN_V3
-	struct {
-		fm_memac_t		fm_memac;
-		fm_memac_mdio_t		fm_memac_mdio;
-	} memac[10];
-	u8			res4[32*1024];
-	fm_memac_mdio_t		fm_dedicated_mdio[2];
-#else
-	struct {
-		fm_dtsec_t	fm_dtesc;
-		fm_mdio_t	fm_mdio;
-	} mac_1g[8];		/* support up to 8 1g controllers */
-	struct {
-		fm_10gec_t		fm_10gec;
-		fm_10gec_mdio_t		fm_10gec_mdio;
-	} mac_10g[1];
-	u8			res4[48*1024];
-#endif
-	fm_1588_t		fm_1588;
-	u8			res5[4*1024];
-} ccsr_fman_t;
-
-#endif /*__FSL_FMAN_H__*/
diff --git a/arch/powerpc/include/asm/fsl_tgec.h b/arch/powerpc/include/asm/fsl_tgec.h
deleted file mode 100644
index 92fb777..0000000
--- a/arch/powerpc/include/asm/fsl_tgec.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- *	Dave Liu <daveliu@freescale.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __TGEC_H__
-#define __TGEC_H__
-
-#include <phy.h>
-
-struct tgec {
-	/* 10GEC general control and status registers */
-	u32	tgec_id;	/* Controller ID register */
-	u32	res0;
-	u32	command_config;	/* Control and configuration register */
-	u32	mac_addr_0;	/* Lower 32 bits of 48-bit MAC address */
-	u32	mac_addr_1;	/* Upper 16 bits of 48-bit MAC address */
-	u32	maxfrm;		/* Maximum frame length register */
-	u32	pause_quant;	/* Pause quanta register */
-	u32	res1[4];
-	u32	hashtable_ctrl;	/* Hash table control register */
-	u32	res2[4];
-	u32	status;		/* MAC status register */
-	u32	tx_ipg_length;	/* Transmitter inter-packet-gap register */
-	u32	mac_addr_2;	/* Lower 32 bits of the 2nd 48-bit MAC addr */
-	u32	mac_addr_3;	/* Upper 16 bits of the 2nd 48-bit MAC addr */
-	u32	res3[4];
-	u32	imask;		/* Interrupt mask register */
-	u32	ievent;		/* Interrupt event register */
-	u32	res4[6];
-	/* 10GEC statistics counter registers */
-	u32	tx_frame_u;	/* Tx frame counter upper */
-	u32	tx_frame_l;	/* Tx frame counter lower */
-	u32	rx_frame_u;	/* Rx frame counter upper */
-	u32	rx_frame_l;	/* Rx frame counter lower */
-	u32	rx_frame_crc_err_u; /* Rx frame check sequence error upper */
-	u32	rx_frame_crc_err_l; /* Rx frame check sequence error lower */
-	u32	rx_align_err_u;	/* Rx alignment error upper */
-	u32	rx_align_err_l;	/* Rx alignment error lower */
-	u32	tx_pause_frame_u; /* Tx valid pause frame upper */
-	u32	tx_pause_frame_l; /* Tx valid pause frame lower */
-	u32	rx_pause_frame_u; /* Rx valid pause frame upper */
-	u32	rx_pause_frame_l; /* Rx valid pause frame upper */
-	u32	rx_long_err_u;	/* Rx too long frame error upper */
-	u32	rx_long_err_l;	/* Rx too long frame error lower */
-	u32	rx_frame_err_u;	/* Rx frame length error upper */
-	u32	rx_frame_err_l;	/* Rx frame length error lower */
-	u32	tx_vlan_u;	/* Tx VLAN frame upper */
-	u32	tx_vlan_l;	/* Tx VLAN frame lower */
-	u32	rx_vlan_u;	/* Rx VLAN frame upper */
-	u32	rx_vlan_l;	/* Rx VLAN frame lower */
-	u32	tx_oct_u;	/* Tx octets upper */
-	u32	tx_oct_l;	/* Tx octets lower */
-	u32	rx_oct_u;	/* Rx octets upper */
-	u32	rx_oct_l;	/* Rx octets lower */
-	u32	rx_uni_u;	/* Rx unicast frame upper */
-	u32	rx_uni_l;	/* Rx unicast frame lower */
-	u32	rx_multi_u;	/* Rx multicast frame upper */
-	u32	rx_multi_l;	/* Rx multicast frame lower */
-	u32	rx_brd_u;	/* Rx broadcast frame upper */
-	u32	rx_brd_l;	/* Rx broadcast frame lower */
-	u32	tx_frame_err_u;	/* Tx frame error upper */
-	u32	tx_frame_err_l;	/* Tx frame error lower */
-	u32	tx_uni_u;	/* Tx unicast frame upper */
-	u32	tx_uni_l;	/* Tx unicast frame lower */
-	u32	tx_multi_u;	/* Tx multicast frame upper */
-	u32	tx_multi_l;	/* Tx multicast frame lower */
-	u32	tx_brd_u;	/* Tx broadcast frame upper */
-	u32	tx_brd_l;	/* Tx broadcast frame lower */
-	u32	rx_drop_u;	/* Rx dropped packets upper */
-	u32	rx_drop_l;	/* Rx dropped packets lower */
-	u32	rx_eoct_u;	/* Rx ethernet octets upper */
-	u32	rx_eoct_l;	/* Rx ethernet octets lower */
-	u32	rx_pkt_u;	/* Rx packets upper */
-	u32	rx_pkt_l;	/* Rx packets lower */
-	u32	tx_undsz_u;	/* Undersized packet upper */
-	u32	tx_undsz_l;	/* Undersized packet lower */
-	u32	rx_64_u;	/* Rx 64 oct packet upper */
-	u32	rx_64_l;	/* Rx 64 oct packet lower */
-	u32	rx_127_u;	/* Rx 65 to 127 oct packet upper */
-	u32	rx_127_l;	/* Rx 65 to 127 oct packet lower */
-	u32	rx_255_u;	/* Rx 128 to 255 oct packet upper */
-	u32	rx_255_l;	/* Rx 128 to 255 oct packet lower */
-	u32	rx_511_u;	/* Rx 256 to 511 oct packet upper */
-	u32	rx_511_l;	/* Rx 256 to 511 oct packet lower */
-	u32	rx_1023_u;	/* Rx 512 to 1023 oct packet upper */
-	u32	rx_1023_l;	/* Rx 512 to 1023 oct packet lower */
-	u32	rx_1518_u;	/* Rx 1024 to 1518 oct packet upper */
-	u32	rx_1518_l;	/* Rx 1024 to 1518 oct packet lower */
-	u32	rx_1519_u;	/* Rx 1519 to max oct packet upper */
-	u32	rx_1519_l;	/* Rx 1519 to max oct packet lower */
-	u32	tx_oversz_u;	/* oversized packet upper */
-	u32	tx_oversz_l;	/* oversized packet lower */
-	u32	tx_jabber_u;	/* Jabber packet upper */
-	u32	tx_jabber_l;	/* Jabber packet lower */
-	u32	tx_frag_u;	/* Fragment packet upper */
-	u32	tx_frag_l;	/* Fragment packet lower */
-	u32	rx_err_u;	/* Rx frame error upper */
-	u32	rx_err_l;	/* Rx frame error lower */
-	u32	res5[0x39a];
-};
-
-/* EC10G_ID - 10-gigabit ethernet MAC controller ID */
-#define EC10G_ID_VER_MASK	0x0000ff00
-#define EC10G_ID_VER_SHIFT	8
-#define EC10G_ID_REV_MASK	0x000000ff
-
-/* COMMAND_CONFIG - command and configuration register */
-#define TGEC_CMD_CFG_EN_TIMESTAMP	0x00100000 /* enable IEEE1588 */
-#define TGEC_CMD_CFG_TX_ADDR_INS_SEL	0x00080000 /* Tx mac addr w/ second */
-#define TGEC_CMD_CFG_NO_LEN_CHK		0x00020000 /* payload len chk disable */
-#define TGEC_CMD_CFG_SEND_IDLE		0x00010000 /* send XGMII idle seqs */
-#define TGEC_CMD_CFG_RX_ER_DISC		0x00004000 /* Rx err frm discard enb */
-#define TGEC_CMD_CFG_CMD_FRM_EN		0x00002000 /* CMD frame RX enable */
-#define TGEC_CMD_CFG_STAT_CLR		0x00001000 /* clear stats */
-#define TGEC_CMD_CFG_TX_ADDR_INS	0x00000200 /* overwrite src MAC addr */
-#define TGEC_CMD_CFG_PAUSE_IGNORE	0x00000100 /* ignore pause frames */
-#define TGEC_CMD_CFG_PAUSE_FWD		0x00000080 /* fwd pause frames */
-#define TGEC_CMD_CFG_CRC_FWD		0x00000040 /* fwd Rx CRC frames */
-#define TGEC_CMD_CFG_PAD_EN		0x00000020 /* MAC remove Rx padding */
-#define TGEC_CMD_CFG_PROM_EN		0x00000010 /* promiscuous mode enable */
-#define TGEC_CMD_CFG_WAN_MODE		0x00000008 /* WAN mode enable */
-#define TGEC_CMD_CFG_RX_EN		0x00000002 /* MAC Rx path enable */
-#define TGEC_CMD_CFG_TX_EN		0x00000001 /* MAC Tx path enable */
-#define TGEC_CMD_CFG_RXTX_EN	(TGEC_CMD_CFG_RX_EN | TGEC_CMD_CFG_TX_EN)
-
-/* HASHTABLE_CTRL - Hashtable control register */
-#define HASHTABLE_CTRL_MCAST_EN	0x00000200 /* enable mulitcast Rx hash */
-#define HASHTABLE_CTRL_ADDR_MASK	0x000001ff
-
-/* TX_IPG_LENGTH - Transmit inter-packet gap length register */
-#define TX_IPG_LENGTH_IPG_LEN_MASK	0x000003ff
-
-/* IMASK - interrupt mask register */
-#define IMASK_MDIO_SCAN_EVENT	0x00010000 /* MDIO scan event mask */
-#define IMASK_MDIO_CMD_CMPL	0x00008000 /* MDIO cmd completion mask */
-#define IMASK_REM_FAULT		0x00004000 /* remote fault mask */
-#define IMASK_LOC_FAULT		0x00002000 /* local fault mask */
-#define IMASK_TX_ECC_ER		0x00001000 /* Tx frame ECC error mask */
-#define IMASK_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow mask */
-#define IMASK_TX_ER		0x00000200 /* Tx frame error mask */
-#define IMASK_RX_FIFO_OVFL	0x00000100 /* Rx FIFO overflow mask */
-#define IMASK_RX_ECC_ER		0x00000080 /* Rx frame ECC error mask */
-#define IMASK_RX_JAB_FRM	0x00000040 /* Rx jabber frame mask */
-#define IMASK_RX_OVRSZ_FRM	0x00000020 /* Rx oversized frame mask */
-#define IMASK_RX_RUNT_FRM	0x00000010 /* Rx runt frame mask */
-#define IMASK_RX_FRAG_FRM	0x00000008 /* Rx fragment frame mask */
-#define IMASK_RX_LEN_ER		0x00000004 /* Rx payload length error mask */
-#define IMASK_RX_CRC_ER		0x00000002 /* Rx CRC error mask */
-#define IMASK_RX_ALIGN_ER	0x00000001 /* Rx alignment error mask */
-
-#define IMASK_MASK_ALL		0x00000000
-
-/* IEVENT - interrupt event register */
-#define IEVENT_MDIO_SCAN_EVENT	0x00010000 /* MDIO scan event */
-#define IEVENT_MDIO_CMD_CMPL	0x00008000 /* MDIO cmd completion */
-#define IEVENT_REM_FAULT	0x00004000 /* remote fault */
-#define IEVENT_LOC_FAULT	0x00002000 /* local fault */
-#define IEVENT_TX_ECC_ER	0x00001000 /* Tx frame ECC error */
-#define IEVENT_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow */
-#define IEVENT_TX_ER		0x00000200 /* Tx frame error */
-#define IEVENT_RX_FIFO_OVFL	0x00000100 /* Rx FIFO overflow */
-#define IEVENT_RX_ECC_ER	0x00000080 /* Rx frame ECC error */
-#define IEVENT_RX_JAB_FRM	0x00000040 /* Rx jabber frame */
-#define IEVENT_RX_OVRSZ_FRM	0x00000020 /* Rx oversized frame */
-#define IEVENT_RX_RUNT_FRM	0x00000010 /* Rx runt frame */
-#define IEVENT_RX_FRAG_FRM	0x00000008 /* Rx fragment frame */
-#define IEVENT_RX_LEN_ER	0x00000004 /* Rx payload length error */
-#define IEVENT_RX_CRC_ER	0x00000002 /* Rx CRC error */
-#define IEVENT_RX_ALIGN_ER	0x00000001 /* Rx alignment error */
-
-#define IEVENT_CLEAR_ALL	0xffffffff
-
-struct tgec_mdio_controller {
-	u32	res0[0xc];
-	u32	mdio_stat;	/* MDIO configuration and status */
-	u32	mdio_ctl;	/* MDIO control */
-	u32	mdio_data;	/* MDIO data */
-	u32	mdio_addr;	/* MDIO address */
-};
-
-#define MDIO_STAT_CLKDIV(x)	(((x>>1) & 0xff) << 8)
-#define MDIO_STAT_BSY		(1 << 0)
-#define MDIO_STAT_RD_ER		(1 << 1)
-#define MDIO_CTL_DEV_ADDR(x)	(x & 0x1f)
-#define MDIO_CTL_PORT_ADDR(x)	((x & 0x1f) << 5)
-#define MDIO_CTL_PRE_DIS	(1 << 10)
-#define MDIO_CTL_SCAN_EN	(1 << 11)
-#define MDIO_CTL_POST_INC	(1 << 14)
-#define MDIO_CTL_READ		(1 << 15)
-
-#define MDIO_DATA(x)		(x & 0xffff)
-#define MDIO_DATA_BSY		(1 << 31)
-
-struct fsl_enet_mac;
-
-void init_tgec(struct fsl_enet_mac *mac, void *base, void *phyregs,
-		int max_rx_len);
-
-#endif
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 0c9d85e..101b8db 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -19,7 +19,7 @@
 #include <fsl_sec.h>
 #include <fsl_sfp.h>
 #include <asm/fsl_lbc.h>
-#include <asm/fsl_fman.h>
+#include <fsl_fman.h>
 #include <fsl_immap.h>
 
 typedef struct ccsr_local {
diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
index 501d4b3..df90476 100644
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -26,7 +26,7 @@
 #include <fsl_mdio.h>
 #include <malloc.h>
 #include <fdt_support.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 
 #include "../common/ngpixis.h"
 #include "../common/fman.h"
diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c
index 396103f..172a55b 100644
--- a/board/freescale/corenet_ds/eth_hydra.c
+++ b/board/freescale/corenet_ds/eth_hydra.c
@@ -55,7 +55,7 @@
 #include <fsl_mdio.h>
 #include <malloc.h>
 #include <fdt_support.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 
 #include "../common/ngpixis.h"
 #include "../common/fman.h"
diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c
index 5cbec7f..c68dc2c 100644
--- a/board/freescale/corenet_ds/eth_p4080.c
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -24,7 +24,7 @@
 
 #include "../common/ngpixis.h"
 #include "../common/fman.h"
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 
 #define EMI_NONE	0xffffffff
 #define EMI_MASK	0xf0000000
diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c
index ad1bffd..62b1635 100644
--- a/board/freescale/corenet_ds/eth_superhydra.c
+++ b/board/freescale/corenet_ds/eth_superhydra.c
@@ -55,7 +55,7 @@
 #include <fsl_mdio.h>
 #include <malloc.h>
 #include <fdt_support.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 
 #include "../common/ngpixis.h"
 #include "../common/fman.h"
diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c
index 56f561a..074b713 100644
--- a/board/freescale/p1023rdb/p1023rdb.c
+++ b/board/freescale/p1023rdb/p1023rdb.c
@@ -26,7 +26,7 @@
 #include <fsl_mdio.h>
 #include <miiphy.h>
 #include <phy.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c
index 532eeac..95fe85b 100644
--- a/board/freescale/p2041rdb/eth.c
+++ b/board/freescale/p2041rdb/eth.c
@@ -19,7 +19,7 @@
 #include <fm_eth.h>
 #include <fsl_mdio.h>
 #include <malloc.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 
 #include "cpld.h"
 #include "../common/fman.h"
diff --git a/board/freescale/t102xqds/eth_t102xqds.c b/board/freescale/t102xqds/eth_t102xqds.c
index 441d6a3..99c23f7 100644
--- a/board/freescale/t102xqds/eth_t102xqds.c
+++ b/board/freescale/t102xqds/eth_t102xqds.c
@@ -21,7 +21,7 @@
 #include <fsl_mdio.h>
 #include <miiphy.h>
 #include <phy.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 #include <asm/fsl_serdes.h>
 #include "../common/qixis.h"
 #include "../common/fman.h"
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c
index 856ec6e..02b283d 100644
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -21,7 +21,7 @@
 #include <fsl_mdio.h>
 #include <miiphy.h>
 #include <phy.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 #include <asm/fsl_serdes.h>
 #include "../common/fman.h"
 
diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c
index 8c82934..8bf34fa 100644
--- a/board/freescale/t1040qds/eth.c
+++ b/board/freescale/t1040qds/eth.c
@@ -17,7 +17,7 @@
 #include <fm_eth.h>
 #include <fsl_mdio.h>
 #include <malloc.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 #include <vsc9953.h>
 
 #include "../common/fman.h"
diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
index 71d0457..52cd112 100644
--- a/board/freescale/t104xrdb/eth.c
+++ b/board/freescale/t104xrdb/eth.c
@@ -11,7 +11,7 @@
 #include <fm_eth.h>
 #include <fsl_mdio.h>
 #include <malloc.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 #include <vsc9953.h>
 
 #include "../common/fman.h"
diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
index b82e9e7..1c0ce24 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -21,7 +21,7 @@
 #include <fsl_mdio.h>
 #include <miiphy.h>
 #include <phy.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 #include <asm/fsl_serdes.h>
 #include <hwconfig.h>
 #include "../common/qixis.h"
diff --git a/board/freescale/t208xrdb/eth_t208xrdb.c b/board/freescale/t208xrdb/eth_t208xrdb.c
index cbbc625..ea51195 100644
--- a/board/freescale/t208xrdb/eth_t208xrdb.c
+++ b/board/freescale/t208xrdb/eth_t208xrdb.c
@@ -21,7 +21,7 @@
 #include <fsl_mdio.h>
 #include <miiphy.h>
 #include <phy.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 #include <asm/fsl_serdes.h>
 
 int board_eth_init(bd_t *bis)
diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index 9b416b1..2dfdcbb 100644
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -21,7 +21,7 @@
 #include <fsl_mdio.h>
 #include <miiphy.h>
 #include <phy.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 #include <asm/fsl_serdes.h>
 #include <hwconfig.h>
 #include "../common/qixis.h"
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index 879bd1a..e563a61 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -23,7 +23,7 @@
 #include <fsl_mdio.h>
 #include <miiphy.h>
 #include <phy.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 #include <asm/fsl_serdes.h>
 #include <hwconfig.h>
 
diff --git a/drivers/net/fm/dtsec.c b/drivers/net/fm/dtsec.c
index 8d3dc0e..b339a84 100644
--- a/drivers/net/fm/dtsec.c
+++ b/drivers/net/fm/dtsec.c
@@ -7,7 +7,7 @@
 #include <common.h>
 #include <asm/types.h>
 #include <asm/io.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 #include <fsl_mdio.h>
 #include <phy.h>
 
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 67c96a2..a768a90 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -13,8 +13,8 @@
 #include <fsl_mdio.h>
 #include <miiphy.h>
 #include <phy.h>
-#include <asm/fsl_dtsec.h>
-#include <asm/fsl_tgec.h>
+#include <fsl_dtsec.h>
+#include <fsl_tgec.h>
 #include <fsl_memac.h>
 
 #include "fm.h"
@@ -370,7 +370,7 @@ static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
 	pram = fm_eth->tx_pram;
 	/* graceful stop transmission of frames */
 	setbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
-	sync();
+	mb();
 }
 
 static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
@@ -380,7 +380,7 @@ static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
 	pram = fm_eth->tx_pram;
 	/* re-enable transmission of frames */
 	clrbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
-	sync();
+	mb();
 }
 
 static int fm_eth_open(struct eth_device *dev, bd_t *bd)
@@ -484,9 +484,9 @@ static int fm_eth_send(struct eth_device *dev, void *buf, int len)
 	muram_writew(&txbd->buf_ptr_hi, 0);
 	out_be32(&txbd->buf_ptr_lo, (u32)buf);
 	muram_writew(&txbd->len, len);
-	sync();
+	mb();
 	muram_writew(&txbd->status, TxBD_READY | TxBD_LAST);
-	sync();
+	mb();
 
 	/* update TxQD, let RISC to send the packet */
 	offset_in = muram_readw(&pram->txqd.offset_in);
@@ -494,7 +494,7 @@ static int fm_eth_send(struct eth_device *dev, void *buf, int len)
 	if (offset_in >= muram_readw(&pram->txqd.bd_ring_size))
 		offset_in = 0;
 	muram_writew(&pram->txqd.offset_in, offset_in);
-	sync();
+	mb();
 
 	/* wait for buffer to be transmitted */
 	for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
@@ -545,7 +545,7 @@ static int fm_eth_recv(struct eth_device *dev)
 		/* clear the RxBDs */
 		muram_writew(&rxbd->status, RxBD_EMPTY);
 		muram_writew(&rxbd->len, 0);
-		sync();
+		mb();
 
 		/* advance RxBD */
 		rxbd++;
@@ -561,7 +561,7 @@ static int fm_eth_recv(struct eth_device *dev)
 		if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
 			offset_out = 0;
 		muram_writew(&pram->rxqd.offset_out, offset_out);
-		sync();
+		mb();
 	}
 	fm_eth->cur_rxbd = (void *)rxbd;
 
diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h
index a9691c6..4090910 100644
--- a/drivers/net/fm/fm.h
+++ b/drivers/net/fm/fm.h
@@ -10,7 +10,7 @@
 #include <common.h>
 #include <phy.h>
 #include <fm_eth.h>
-#include <asm/fsl_fman.h>
+#include <fsl_fman.h>
 
 /* Port ID */
 #define OH_PORT_ID_BASE		0x01
diff --git a/drivers/net/fm/tgec.c b/drivers/net/fm/tgec.c
index 5017123..8d4622f 100644
--- a/drivers/net/fm/tgec.c
+++ b/drivers/net/fm/tgec.c
@@ -12,7 +12,7 @@
 #include <phy.h>
 #include <asm/types.h>
 #include <asm/io.h>
-#include <asm/fsl_tgec.h>
+#include <fsl_tgec.h>
 
 #include "fm.h"
 
diff --git a/drivers/net/fm/tgec_phy.c b/drivers/net/fm/tgec_phy.c
index 095f00c..24cb17b 100644
--- a/drivers/net/fm/tgec_phy.c
+++ b/drivers/net/fm/tgec_phy.c
@@ -9,7 +9,7 @@
 #include <miiphy.h>
 #include <phy.h>
 #include <asm/io.h>
-#include <asm/fsl_tgec.h>
+#include <fsl_tgec.h>
 #include <fm_eth.h>
 
 /*
diff --git a/include/fsl_dtsec.h b/include/fsl_dtsec.h
new file mode 100644
index 0000000..41b8398
--- /dev/null
+++ b/include/fsl_dtsec.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DTSEC_H__
+#define __DTSEC_H__
+
+#include <asm/types.h>
+
+struct dtsec {
+	u32	tsec_id;	/* controller ID and version */
+	u32	tsec_id2;	/* controller ID and configuration */
+	u32	ievent;		/* interrupt event */
+	u32	imask;		/* interrupt mask */
+	u32	res0;
+	u32	ecntrl;		/* ethernet control and configuration */
+	u32	ptv;		/* pause time value */
+	u32	tbipa;		/* TBI PHY address */
+	u32	res1[8];
+	u32	tctrl;		/* Transmit control register */
+	u32	res2[3];
+	u32	rctrl;		/* Receive control register */
+	u32	res3[11];
+	u32	igaddr[8];	/* Individual group address */
+	u32	gaddr[8];	/* group address */
+	u32	res4[16];
+	u32	maccfg1;	/* MAC configuration register 1 */
+	u32	maccfg2;	/* MAC configuration register 2 */
+	u32	ipgifg;		/* inter-packet/inter-frame gap */
+	u32	hafdup;		/* half-duplex control */
+	u32	maxfrm;		/* Maximum frame size */
+	u32	res5[3];
+	u32	miimcfg;	/* MII management configuration */
+	u32	miimcom;	/* MII management command */
+	u32	miimadd;	/* MII management address */
+	u32	miimcon;	/* MII management control */
+	u32	miimstat;	/* MII management status */
+	u32	miimind;	/* MII management indicator */
+	u32	res6;
+	u32	ifstat;		/* Interface status */
+	u32	macstnaddr1;	/* MAC station address 1 */
+	u32	macstnaddr2;	/* MAC station address 2 */
+	u32	res7[46];
+	/* transmit and receive counter */
+	u32	tr64;		/* Tx and Rx 64 bytes frame */
+	u32	tr127;		/* Tx and Rx 65 to 127 bytes frame */
+	u32	tr255;		/* Tx and Rx 128 to 255 bytes frame */
+	u32	tr511;		/* Tx and Rx 256 to 511 bytes frame */
+	u32	tr1k;		/* Tx and Rx 512 to 1023 bytes frame */
+	u32	trmax;		/* Tx and Rx 1024 to 1518 bytes frame */
+	u32	trmgv;		/* Tx and Rx 1519 to 1522 good VLAN frame */
+	/* receive counters */
+	u32	rbyt;		/* Receive byte counter */
+	u32	rpkt;		/* Receive packet counter */
+	u32	rfcs;		/* Receive FCS error */
+	u32	rmca;		/* Receive multicast packet */
+	u32	rbca;		/* Receive broadcast packet */
+	u32	rxcf;		/* Receive control frame */
+	u32	rxpf;		/* Receive pause frame */
+	u32	rxuo;		/* Receive unknown OP code */
+	u32	raln;		/* Receive alignment error */
+	u32	rflr;		/* Receive frame length error */
+	u32	rcde;		/* Receive code error */
+	u32	rcse;		/* Receive carrier sense error */
+	u32	rund;		/* Receive undersize packet */
+	u32	rovr;		/* Receive oversize packet */
+	u32	rfrg;		/* Receive fragments counter */
+	u32	rjbr;		/* Receive jabber counter */
+	u32	rdrp;		/* Receive drop counter */
+	/* transmit counters */
+	u32	tbyt;		/* Transmit byte counter */
+	u32	tpkt;		/* Transmit packet */
+	u32	tmca;		/* Transmit multicast packet */
+	u32	tbca;		/* Transmit broadcast packet */
+	u32	txpf;		/* Transmit pause control frame */
+	u32	tdfr;		/* Transmit deferral packet */
+	u32	tedf;		/* Transmit excessive deferral pkt */
+	u32	tscl;		/* Transmit single collision pkt */
+	u32	tmcl;		/* Transmit multiple collision pkt */
+	u32	tlcl;		/* Transmit late collision pkt */
+	u32	txcl;		/* Transmit excessive collision */
+	u32	tncl;		/* Transmit total collision */
+	u32	res8;
+	u32	tdrp;		/* Transmit drop frame */
+	u32	tjbr;		/* Transmit jabber frame */
+	u32	tfcs;		/* Transmit FCS error */
+	u32	txcf;		/* Transmit control frame */
+	u32	tovr;		/* Transmit oversize frame */
+	u32	tund;		/* Transmit undersize frame */
+	u32	tfrg;		/* Transmit fragments frame */
+	/* counter controls */
+	u32	car1;		/* carry register 1 */
+	u32	car2;		/* carry register 2 */
+	u32	cam1;		/* carry register 1 mask */
+	u32	cam2;		/* carry register 2 mask */
+	u32	res9[80];
+};
+
+
+/* TBI register addresses */
+#define TBI_CR			0x00
+#define TBI_SR			0x01
+#define TBI_ANA			0x04
+#define TBI_ANLPBPA		0x05
+#define TBI_ANEX		0x06
+#define TBI_TBICON		0x11
+
+/* TBI MDIO register bit fields*/
+#define TBICON_CLK_SELECT	0x0020
+#define TBIANA_ASYMMETRIC_PAUSE 0x0100
+#define TBIANA_SYMMETRIC_PAUSE  0x0080
+#define TBIANA_HALF_DUPLEX	0x0040
+#define TBIANA_FULL_DUPLEX	0x0020
+#define TBICR_PHY_RESET		0x8000
+#define TBICR_ANEG_ENABLE	0x1000
+#define TBICR_RESTART_ANEG	0x0200
+#define TBICR_FULL_DUPLEX	0x0100
+#define TBICR_SPEED1_SET	0x0040
+
+/* IEVENT - interrupt events register */
+#define IEVENT_BABR	0x80000000 /* Babbling receive error */
+#define IEVENT_RXC	0x40000000 /* pause control frame received */
+#define IEVENT_MSRO	0x04000000 /* MIB counter overflow */
+#define IEVENT_GTSC	0x02000000 /* Graceful transmit stop complete */
+#define IEVENT_BABT	0x01000000 /* Babbling transmit error */
+#define IEVENT_TXC	0x00800000 /* control frame transmitted */
+#define IEVENT_TXE	0x00400000 /* Transmit channel error */
+#define IEVENT_LC	0x00040000 /* Late collision occurred */
+#define IEVENT_CRL	0x00020000 /* Collision retry exceed limit */
+#define IEVENT_XFUN	0x00010000 /* Transmit FIFO underrun */
+#define IEVENT_ABRT	0x00008000 /* Transmit packet abort */
+#define IEVENT_MMRD	0x00000400 /* MII management read complete */
+#define IEVENT_MMWR	0x00000200 /* MII management write complete */
+#define IEVENT_GRSC	0x00000100 /* Graceful stop complete */
+#define IEVENT_TDPE	0x00000002 /* Internal data parity error on Tx */
+#define IEVENT_RDPE	0x00000001 /* Internal data parity error on Rx */
+
+#define IEVENT_CLEAR_ALL	0xffffffff
+
+/* IMASK - interrupt mask register */
+#define IMASK_BREN	0x80000000 /* Babbling receive enable */
+#define IMASK_RXCEN	0x40000000 /* receive control enable */
+#define IMASK_MSROEN	0x04000000 /* MIB counter overflow enable */
+#define IMASK_GTSCEN	0x02000000 /* Graceful Tx stop complete enable */
+#define IMASK_BTEN	0x01000000 /* Babbling transmit error enable */
+#define IMASK_TXCEN	0x00800000 /* control frame transmitted enable */
+#define IMASK_TXEEN	0x00400000 /* Transmit channel error enable */
+#define IMASK_LCEN	0x00040000 /* Late collision interrupt enable */
+#define IMASK_CRLEN	0x00020000 /* Collision retry exceed limit */
+#define IMASK_XFUNEN	0x00010000 /* Transmit FIFO underrun enable */
+#define IMASK_ABRTEN	0x00008000 /* Transmit packet abort enable */
+#define IMASK_MMRDEN	0x00000400 /* MII management read complete enable */
+#define IMASK_MMWREN	0x00000200 /* MII management write complete enable */
+#define IMASK_GRSCEN	0x00000100 /* Graceful stop complete interrupt enable */
+#define IMASK_TDPEEN	0x00000002 /* Internal data parity error on Tx enable */
+#define IMASK_RDPEEN	0x00000001 /* Internal data parity error on Rx enable */
+
+#define IMASK_MASK_ALL	0x00000000
+
+/* ECNTRL - ethernet control register */
+#define ECNTRL_CFG_RO	0x80000000 /* GMIIM, RPM, R100M, SGMIIM bits are RO */
+#define ECNTRL_CLRCNT	0x00004000 /* clear all statistics */
+#define ECNTRL_AUTOZ	0x00002000 /* auto zero MIB counter */
+#define ECNTRL_STEN	0x00001000 /* enable internal counters to update */
+#define ECNTRL_GMIIM	0x00000040 /* 1- GMII or RGMII interface mode */
+#define ECNTRL_TBIM	0x00000020 /* 1- Ten-bit interface mode */
+#define ECNTRL_RPM	0x00000010 /* 1- RGMII reduced-pin mode */
+#define ECNTRL_R100M	0x00000008 /* 1- RGMII 100 Mbps, SGMII 100 Mbps
+				      0- RGMII 10 Mbps, SGMII 10 Mbps */
+#define ECNTRL_SGMIIM	0x00000002 /* 1- SGMII interface mode */
+#define ECNTRL_TBIM	0x00000020 /* 1- TBI Interface mode (for SGMII) */
+
+#define ECNTRL_DEFAULT	(ECNTRL_TBIM | ECNTRL_R100M | ECNTRL_SGMIIM)
+
+/* TCTRL - Transmit control register */
+#define TCTRL_THDF	0x00000800 /* Transmit half-duplex flow control */
+#define TCTRL_TTSE	0x00000040 /* Transmit time-stamp enable */
+#define TCTRL_GTS	0x00000020 /* Graceful transmit stop */
+#define TCTRL_RFC_PAUSE	0x00000010 /* Receive flow control pause frame */
+
+/* RCTRL - Receive control register */
+#define RCTRL_PAL_MASK	0x001f0000 /* packet alignment padding length */
+#define RCTRL_PAL_SHIFT	16
+#define RCTRL_CFA	0x00008000 /* control frame accept enable */
+#define RCTRL_GHTX	0x00000800 /* group address hash table extend */
+#define RCTRL_RTSE	0x00000040 /* receive 1588 time-stamp enable */
+#define RCTRL_GRS	0x00000020 /* graceful receive stop */
+#define RCTRL_BC_REJ	0x00000010 /* broadcast frame reject */
+#define RCTRL_BC_MPROM	0x00000008 /* all multicast/broadcast frames received */
+#define RCTRL_RSF	0x00000004 /* receive short frame(17~63 bytes) enable */
+#define RCTRL_EMEN	0x00000002 /* Exact match MAC address enable */
+#define RCTRL_UPROM	0x00000001 /* all unicast frame received */
+
+/* MACCFG1 - MAC configuration 1 register */
+#define MACCFG1_SOFT_RST	0x80000000 /* place the MAC in reset */
+#define MACCFG1_RST_RXMAC	0x00080000 /* reset receive MAC control block */
+#define MACCFG1_RST_TXMAC	0x00040000 /* reet transmit MAC control block */
+#define MACCFG1_RST_RXFUN	0x00020000 /* reset receive function block */
+#define MACCFG1_RST_TXFUN	0x00010000 /* reset transmit function block */
+#define MACCFG1_LOOPBACK	0x00000100 /* MAC loopback */
+#define MACCFG1_RX_FLOW		0x00000020 /* Receive flow */
+#define MACCFG1_TX_FLOW		0x00000010 /* Transmit flow */
+#define MACCFG1_SYNC_RXEN	0x00000008 /* Frame reception enabled */
+#define MACCFG1_RX_EN		0x00000004 /* Rx enable */
+#define MACCFG1_SYNC_TXEN	0x00000002 /* Frame transmission is enabled */
+#define MACCFG1_TX_EN		0x00000001 /* Tx enable */
+#define MACCFG1_RXTX_EN		(MACCFG1_RX_EN | MACCFG1_TX_EN)
+
+/* MACCFG2 - MAC configuration 2 register */
+#define MACCFG2_PRE_LEN_MASK	0x0000f000 /* preamble length */
+#define MACCFG2_PRE_LEN(x)	((x << 12) & MACCFG2_PRE_LEN_MASK)
+#define MACCFG2_IF_MODE_MASK	0x00000300
+#define MACCFG2_IF_MODE_NIBBLE	0x00000100 /* MII, 10/100 Mbps MII/RMII */
+#define MACCFG2_IF_MODE_BYTE	0x00000200 /* GMII/TBI, 1000 GMII/TBI */
+#define MACCFG2_PRE_RX_EN	0x00000080 /* receive preamble enable */
+#define MACCFG2_PRE_TX_EN	0x00000040 /* tx preable enable */
+#define MACCFG2_HUGE_FRAME	0x00000020 /* >= max frame len enable */
+#define MACCFG2_LEN_CHECK	0x00000010 /* MAC check frame's length Rx */
+#define MACCFG2_MAG_EN		0x00000008 /* magic packet enable */
+#define MACCFG2_PAD_CRC		0x00000004 /* pad and append CRC */
+#define MACCFG2_CRC_EN		0x00000002 /* MAC appends a CRC on all frames */
+#define MACCFG2_FULL_DUPLEX	0x00000001 /* Full deplex mode */
+
+struct fsl_enet_mac;
+
+void init_dtsec(struct fsl_enet_mac *mac, void *base, void *phyregs,
+		int max_rx_len);
+
+#endif
diff --git a/include/fsl_fman.h b/include/fsl_fman.h
new file mode 100644
index 0000000..4d04415
--- /dev/null
+++ b/include/fsl_fman.h
@@ -0,0 +1,463 @@
+/*
+ * MPC85xx Internal Memory Map
+ *
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_FMAN_H__
+#define __FSL_FMAN_H__
+
+#include <asm/types.h>
+
+typedef struct fm_bmi_common {
+	u32	fmbm_init;	/* BMI initialization */
+	u32	fmbm_cfg1;	/* BMI configuration1 */
+	u32	fmbm_cfg2;	/* BMI configuration2 */
+	u32	res0[0x5];
+	u32	fmbm_ievr;	/* interrupt event register */
+	u32	fmbm_ier;	/* interrupt enable register */
+	u32	fmbm_ifr;	/* interrupt force register */
+	u32	res1[0x5];
+	u32	fmbm_arb[0x8];	/* BMI arbitration */
+	u32	res2[0x28];
+	u32	fmbm_gde;	/* global debug enable */
+	u32	fmbm_pp[0x3f];	/* BMI port parameters */
+	u32	res3;
+	u32	fmbm_pfs[0x3f];	/* BMI port FIFO size */
+	u32	res4;
+	u32	fmbm_ppid[0x3f];/* port partition ID */
+} fm_bmi_common_t;
+
+typedef struct fm_qmi_common {
+	u32	fmqm_gc;	/* general configuration register */
+	u32	res0;
+	u32	fmqm_eie;	/* error interrupt event register */
+	u32	fmqm_eien;	/* error interrupt enable register */
+	u32	fmqm_eif;	/* error interrupt force register */
+	u32	fmqm_ie;	/* interrupt event register */
+	u32	fmqm_ien;	/* interrupt enable register */
+	u32	fmqm_if;	/* interrupt force register */
+	u32	fmqm_gs;	/* global status register */
+	u32	fmqm_ts;	/* task status register */
+	u32	fmqm_etfc;	/* enqueue total frame counter */
+	u32	fmqm_dtfc;	/* dequeue total frame counter */
+	u32	fmqm_dc0;	/* dequeue counter 0 */
+	u32	fmqm_dc1;	/* dequeue counter 1 */
+	u32	fmqm_dc2;	/* dequeue counter 2 */
+	u32	fmqm_dc3;	/* dequeue counter 3 */
+	u32	fmqm_dfnoc;	/* dequeue FQID not override counter */
+	u32	fmqm_dfcc;	/* dequeue FQID from context counter */
+	u32	fmqm_dffc;	/* dequeue FQID from FD counter */
+	u32	fmqm_dcc;	/* dequeue confirm counter */
+	u32	res1[0xc];
+	u32	fmqm_dtrc;	/* debug trap configuration register */
+	u32	fmqm_efddd;	/* enqueue frame descriptor dynamic debug */
+	u32	res3[0x2];
+	u32	res4[0xdc];	/* missing debug regs */
+} fm_qmi_common_t;
+
+typedef struct fm_bmi {
+	u8	res[1024];
+} fm_bmi_t;
+
+typedef struct fm_qmi {
+	u8	res[1024];
+} fm_qmi_t;
+
+struct fm_bmi_rx_port {
+	u32 fmbm_rcfg;	/* Rx configuration */
+	u32 fmbm_rst;	/* Rx status */
+	u32 fmbm_rda;	/* Rx DMA attributes */
+	u32 fmbm_rfp;	/* Rx FIFO parameters */
+	u32 fmbm_rfed;	/* Rx frame end data */
+	u32 fmbm_ricp;	/* Rx internal context parameters */
+	u32 fmbm_rim;	/* Rx internal margins */
+	u32 fmbm_rebm;	/* Rx external buffer margins */
+	u32 fmbm_rfne;	/* Rx frame next engine */
+	u32 fmbm_rfca;	/* Rx frame command attributes */
+	u32 fmbm_rfpne;	/* Rx frame parser next engine */
+	u32 fmbm_rpso;	/* Rx parse start offset */
+	u32 fmbm_rpp;	/* Rx policer profile */
+	u32 fmbm_rccb;	/* Rx coarse classification base */
+	u32 res1[0x2];
+	u32 fmbm_rprai[0x8];	/* Rx parse results array Initialization */
+	u32 fmbm_rfqid;		/* Rx frame queue ID */
+	u32 fmbm_refqid;	/* Rx error frame queue ID */
+	u32 fmbm_rfsdm;		/* Rx frame status discard mask */
+	u32 fmbm_rfsem;		/* Rx frame status error mask */
+	u32 fmbm_rfene;		/* Rx frame enqueue next engine */
+	u32 res2[0x23];
+	u32 fmbm_ebmpi[0x8];	/* buffer manager pool information */
+	u32 fmbm_acnt[0x8];	/* allocate counter */
+	u32 res3[0x8];
+	u32 fmbm_cgm[0x8];	/* congestion group map */
+	u32 fmbm_mpd;		/* BMan pool depletion */
+	u32 res4[0x1F];
+	u32 fmbm_rstc;		/* Rx statistics counters */
+	u32 fmbm_rfrc;		/* Rx frame counters */
+	u32 fmbm_rfbc;		/* Rx bad frames counter */
+	u32 fmbm_rlfc;		/* Rx large frames counter */
+	u32 fmbm_rffc;		/* Rx filter frames counter */
+	u32 fmbm_rfdc;		/* Rx frame discard counter */
+	u32 fmbm_rfldec;	/* Rx frames list DMA error counter */
+	u32 fmbm_rodc;		/* Rx out of buffers discard counter */
+	u32 fmbm_rbdc;		/* Rx buffers deallocate counter */
+	u32 res5[0x17];
+	u32 fmbm_rpc;		/* Rx performance counters */
+	u32 fmbm_rpcp;		/* Rx performance count parameters */
+	u32 fmbm_rccn;		/* Rx cycle counter */
+	u32 fmbm_rtuc;		/* Rx tasks utilization counter */
+	u32 fmbm_rrquc;		/* Rx receive queue utilization counter */
+	u32 fmbm_rduc;		/* Rx DMA utilization counter */
+	u32 fmbm_rfuc;		/* Rx FIFO utilization counter */
+	u32 fmbm_rpac;		/* Rx pause activation counter */
+	u32 res6[0x18];
+	u32 fmbm_rdbg;		/* Rx debug configuration */
+};
+
+/* FMBM_RCFG - Rx configuration */
+#define FMBM_RCFG_EN		0x80000000 /* port is enabled to receive data */
+#define FMBM_RCFG_FDOVR		0x02000000 /* frame discard override */
+#define FMBM_RCFG_IM		0x01000000 /* independent mode */
+
+/* FMBM_RST - Rx status */
+#define FMBM_RST_BSY		0x80000000 /* Rx port is busy */
+
+/* FMBM_RFCA - Rx frame command attributes */
+#define FMBM_RFCA_ORDER		0x80000000
+#define FMBM_RFCA_MR_MASK	0x003f0000
+#define FMBM_RFCA_MR(x)		((x << 16) & FMBM_RFCA_MR_MASK)
+
+/* FMBM_RSTC - Rx statistics */
+#define FMBM_RSTC_EN		0x80000000 /* statistics counters enable */
+
+struct fm_bmi_tx_port {
+	u32 fmbm_tcfg;	/* Tx configuration */
+	u32 fmbm_tst;	/* Tx status */
+	u32 fmbm_tda;	/* Tx DMA attributes */
+	u32 fmbm_tfp;	/* Tx FIFO parameters */
+	u32 fmbm_tfed;	/* Tx frame end data */
+	u32 fmbm_ticp;	/* Tx internal context parameters */
+	u32 fmbm_tfne;	/* Tx frame next engine */
+	u32 fmbm_tfca;	/* Tx frame command attributes */
+	u32 fmbm_tcfqid;/* Tx confirmation frame queue ID */
+	u32 fmbm_tfeqid;/* Tx error frame queue ID */
+	u32 fmbm_tfene;	/* Tx frame enqueue next engine */
+	u32 fmbm_trlmts;/* Tx rate limiter scale */
+	u32 fmbm_trlmt;	/* Tx rate limiter */
+	u32 res0[0x73];
+	u32 fmbm_tstc;	/* Tx statistics counters */
+	u32 fmbm_tfrc;	/* Tx frame counter */
+	u32 fmbm_tfdc;	/* Tx frames discard counter */
+	u32 fmbm_tfledc;/* Tx frame length error discard counter */
+	u32 fmbm_tfufdc;/* Tx frame unsupported format discard counter */
+	u32 fmbm_tbdc;	/* Tx buffers deallocate counter */
+	u32 res1[0x1a];
+	u32 fmbm_tpc;	/* Tx performance counters */
+	u32 fmbm_tpcp;	/* Tx performance count parameters */
+	u32 fmbm_tccn;	/* Tx cycle counter */
+	u32 fmbm_ttuc;	/* Tx tasks utilization counter */
+	u32 fmbm_ttcquc;/* Tx transmit confirm queue utilization counter */
+	u32 fmbm_tduc;	/* Tx DMA utilization counter */
+	u32 fmbm_tfuc;	/* Tx FIFO utilization counter */
+	u32 res2[0x19];
+	u32 fmbm_tdcfg;	/* Tx debug configuration */
+};
+
+/* FMBM_TCFG - Tx configuration */
+#define FMBM_TCFG_EN	0x80000000 /* port is enabled to transmit data */
+#define FMBM_TCFG_IM	0x01000000 /* independent mode enable */
+
+/* FMBM_TST - Tx status */
+#define FMBM_TST_BSY		0x80000000 /* Tx port is busy */
+
+/* FMBM_TFCA - Tx frame command attributes */
+#define FMBM_TFCA_ORDER		0x80000000
+#define FMBM_TFCA_MR_MASK	0x003f0000
+#define FMBM_TFCA_MR(x)		((x << 16) & FMBM_TFCA_MR_MASK)
+
+/* FMBM_TSTC - Tx statistics counters */
+#define FMBM_TSTC_EN		0x80000000
+
+/* FMBM_INIT - BMI initialization register */
+#define FMBM_INIT_START		0x80000000 /* init internal buffers */
+
+/* FMBM_CFG1 - BMI configuration 1 */
+#define FMBM_CFG1_FBPS_MASK	0x03ff0000 /* Free buffer pool size */
+#define FMBM_CFG1_FBPS_SHIFT	16
+#define FMBM_CFG1_FBPO_MASK	0x000003ff /* Free buffer pool offset */
+
+/* FMBM_IEVR - interrupt event */
+#define FMBM_IEVR_PEC		0x80000000 /* pipeline table ECC err detected */
+#define FMBM_IEVR_LEC		0x40000000 /* linked list RAM ECC error */
+#define FMBM_IEVR_SEC		0x20000000 /* statistics count RAM ECC error */
+#define FMBM_IEVR_CLEAR_ALL	(FMBM_IEVR_PEC | FMBM_IEVR_LEC | FMBM_IEVR_SEC)
+
+/* FMBM_IER - interrupt enable */
+#define FMBM_IER_PECE		0x80000000 /* PEC interrupt enable */
+#define FMBM_IER_LECE		0x40000000 /* LEC interrupt enable */
+#define FMBM_IER_SECE		0x20000000 /* SEC interrupt enable */
+
+#define FMBM_IER_DISABLE_ALL	0x00000000
+
+/* FMBM_PP - BMI Port Parameters */
+#define FMBM_PP_MXT_MASK	0x3f000000 /* Max # tasks */
+#define FMBM_PP_MXT(x)		(((x-1) << 24) & FMBM_PP_MXT_MASK)
+#define FMBM_PP_MXD_MASK	0x00000f00 /* Max DMA */
+#define FMBM_PP_MXD(x)		(((x-1) << 8) & FMBM_PP_MXD_MASK)
+
+/* FMBM_PFS - BMI Port FIFO Size */
+#define FMBM_PFS_IFSZ_MASK	0x000003ff /* Internal Fifo Size */
+#define FMBM_PFS_IFSZ(x)	(x & FMBM_PFS_IFSZ_MASK)
+
+/* FMQM_GC - global configuration */
+#define FMQM_GC_ENQ_EN		0x80000000 /* enqueue enable */
+#define FMQM_GC_DEQ_EN		0x40000000 /* dequeue enable */
+#define FMQM_GC_STEN		0x10000000 /* enable global stat counters */
+#define FMQM_GC_ENQ_THR_MASK	0x00003f00 /* max number of enqueue Tnum */
+#define FMQM_GC_ENQ(x)		((x << 8) &  FMQM_GC_ENQ_THR_MAS)
+#define FMQM_GC_DEQ_THR_MASK	0x0000003f /* max number of dequeue Tnum */
+#define FMQM_GC_DEQ(x)		(x & FMQM_GC_DEQ_THR_MASK)
+
+/* FMQM_EIE - error interrupt event register */
+#define FMQM_EIE_DEE		0x80000000 /* double-bit ECC error */
+#define FMQM_EIE_DFUPE		0x40000000 /* dequeue from unknown PortID */
+#define FMQM_EIE_CLEAR_ALL	(FMQM_EIE_DEE | FMQM_EIE_DFUPE)
+
+/* FMQM_EIEN - error interrupt enable register */
+#define FMQM_EIEN_DEEN		0x80000000 /* double-bit ECC error */
+#define FMQM_EIEN_DFUPEN	0x40000000 /* dequeue from unknown PortID */
+#define FMQM_EIEN_DISABLE_ALL	0x00000000
+
+/* FMQM_IE - interrupt event register */
+#define FMQM_IE_SEE		0x80000000 /* single-bit ECC error detected */
+#define FMQM_IE_CLEAR_ALL	FMQM_IE_SEE
+
+/* FMQM_IEN - interrupt enable register */
+#define FMQM_IEN_SEE		0x80000000 /* single-bit ECC err IRQ enable */
+#define FMQM_IEN_DISABLE_ALL	0x00000000
+
+/* NIA - next invoked action */
+#define NIA_ENG_RISC		0x00000000
+#define NIA_ENG_MASK		0x007c0000
+
+/* action code */
+#define NIA_RISC_AC_CC		0x00000006
+#define NIA_RISC_AC_IM_TX	0x00000008 /* independent mode Tx */
+#define NIA_RISC_AC_IM_RX	0x0000000a /* independent mode Rx */
+#define NIA_RISC_AC_HC		0x0000000c
+
+typedef struct fm_parser {
+	u8	res[1024];
+} fm_parser_t;
+
+typedef struct fm_policer {
+	u8	res[4*1024];
+} fm_policer_t;
+
+typedef struct fm_keygen {
+	u8	res[4*1024];
+} fm_keygen_t;
+
+typedef struct fm_dma {
+	u32	fmdmsr;		/* status register */
+	u32	fmdmmr;		/* mode register */
+	u32	fmdmtr;		/* bus threshold register */
+	u32	fmdmhy;		/* bus hysteresis register */
+	u32	fmdmsetr;	/* SOS emergency threshold register */
+	u32	fmdmtah;	/* transfer bus address high register */
+	u32	fmdmtal;	/* transfer bus address low register */
+	u32	fmdmtcid;	/* transfer bus communication ID register */
+	u32	fmdmra;		/* DMA bus internal ram address register */
+	u32	fmdmrd;		/* DMA bus internal ram data register */
+	u32	res0[0xb];
+	u32	fmdmdcr;	/* debug counter */
+	u32	fmdmemsr;	/* emrgency smoother register */
+	u32	res1;
+	u32	fmdmplr[32];	/* FM DMA PID-LIODN # register */
+	u32	res[0x3c8];
+} fm_dma_t;
+
+/* FMDMSR - Fman DMA status register */
+#define FMDMSR_CMDQNE		0x10000000 /* command queue not empty */
+#define FMDMSR_BER		0x08000000 /* bus err event occurred on bus */
+#define FMDMSR_RDB_ECC		0x04000000 /* read buffer ECC error */
+#define FMDMSR_WRB_SECC		0x02000000 /* write buf ECC err sys side */
+#define FMDMSR_WRB_FECC		0x01000000 /* write buf ECC err Fman side */
+#define FMDMSR_DPEXT_SECC	0x00800000 /* DP external ECC err sys side */
+#define FMDMSR_DPEXT_FECC	0x00400000 /* DP external ECC err Fman side */
+#define FMDMSR_DPDAT_SECC	0x00200000 /* DP data ECC err on sys side */
+#define FMDMSR_DPDAT_FECC	0x00100000 /* DP data ECC err on Fman side */
+#define FMDMSR_SPDAT_FECC	0x00080000 /* SP data ECC error Fman side */
+
+#define FMDMSR_CLEAR_ALL	(FMDMSR_BER | FMDMSR_RDB_ECC \
+				| FMDMSR_WRB_SECC | FMDMSR_WRB_FECC \
+				| FMDMSR_DPEXT_SECC | FMDMSR_DPEXT_FECC \
+				| FMDMSR_DPDAT_SECC | FMDMSR_DPDAT_FECC \
+				| FMDMSR_SPDAT_FECC)
+
+/* FMDMMR - FMan DMA mode register */
+#define FMDMMR_SBER		0x10000000 /* stop the DMA if a bus error */
+
+typedef struct fm_fpm {
+	u32	fpmtnc;		/* TNUM control */
+	u32	fpmprc;		/* Port_ID control */
+	u32	res0;
+	u32	fpmflc;		/* flush control */
+	u32	fpmdis1;	/* dispatch thresholds1 */
+	u32	fpmdis2;	/* dispatch thresholds2 */
+	u32	fmepi;		/* error pending interrupts */
+	u32	fmrie;		/* rams interrupt enable */
+	u32	fpmfcevent[0x4];/* FMan controller event 0-3 */
+	u32	res1[0x4];
+	u32	fpmfcmask[0x4];	/* FMan controller mask 0-3 */
+	u32	res2[0x4];
+	u32	fpmtsc1;	/* timestamp control1 */
+	u32	fpmtsc2;	/* timestamp control2 */
+	u32	fpmtsp;		/* time stamp */
+	u32	fpmtsf;		/* time stamp fraction */
+	u32	fpmrcr;		/* rams control and event */
+	u32	res3[0x3];
+	u32	fpmdrd[0x4];	/* data_ram data 0-3 */
+	u32	res4[0xc];
+	u32	fpmdra;		/* data ram access */
+	u32	fm_ip_rev_1;	/* IP block revision 1 */
+	u32	fm_ip_rev_2;	/* IP block revision 2 */
+	u32	fmrstc;		/* reset command */
+	u32	fmcld;		/* classifier debug control */
+	u32	fmnpi;		/* normal pending interrupts */
+	u32	res5;
+	u32	fmfpee;		/* event and enable */
+	u32	fpmcev[0x4];	/* CPU event 0-3 */
+	u32	res6[0x4];
+	u32	fmfp_ps[0x40];	/* port status */
+	u32	res7[0x260];
+	u32	fpmts[0x80];	/* task status */
+	u32	res8[0xa0];
+} fm_fpm_t;
+
+/* FMFP_PRC - FPM Port_ID Control Register */
+#define FMFPPRC_PORTID_MASK	0x3f000000
+#define FMFPPRC_PORTID_SHIFT	24
+#define FMFPPRC_ORA_SHIFT	16
+#define FMFPPRC_RISC1		0x00000001
+#define FMFPPRC_RISC2		0x00000002
+#define FMFPPRC_RISC_ALL	(FMFPPRC_RISC1 | FMFPPRC_RSIC2)
+
+/* FPM Flush Control Register */
+#define FMFP_FLC_DISP_LIM_NONE	0x00000000 /* no dispatch limitation */
+
+/* FMFP_EE - FPM event and enable register */
+#define FMFPEE_DECC		0x80000000 /* double ECC err on FPM ram */
+#define FMFPEE_STL		0x40000000 /* stall of task ... */
+#define FMFPEE_SECC		0x20000000 /* single ECC error */
+#define FMFPEE_RFM		0x00010000 /* release FMan */
+#define FMFPEE_DECC_EN		0x00008000 /* double ECC interrupt enable */
+#define FMFPEE_STL_EN		0x00004000 /* stall of task interrupt enable */
+#define FMFPEE_SECC_EN		0x00002000 /* single ECC err interrupt enable */
+#define FMFPEE_EHM		0x00000008 /* external halt enable */
+#define FMFPEE_UEC		0x00000004 /* FMan is not halted */
+#define FMFPEE_CER		0x00000002 /* only errornous task stalled */
+#define FMFPEE_DER		0x00000001 /* DMA error is just reported */
+
+#define FMFPEE_CLEAR_EVENT	(FMFPEE_DECC | FMFPEE_STL | FMFPEE_SECC | \
+				 FMFPEE_EHM | FMFPEE_UEC | FMFPEE_CER | \
+				 FMFPEE_DER | FMFPEE_RFM)
+
+/* FMFP_RCR - FMan Rams Control and Event */
+#define FMFP_RCR_MDEC		0x00008000 /* double ECC error in muram */
+#define FMFP_RCR_IDEC		0x00004000 /* double ECC error in iram */
+
+typedef struct fm_imem {
+	u32	iadd;		/* instruction address register */
+	u32	idata;		/* instruction data register */
+	u32	itcfg;		/* timing config register */
+	u32	iready;		/* ready register */
+	u8	res[0xff0];
+} fm_imem_t;
+#define IRAM_IADD_AIE		0x80000000 /* address auto increase enable */
+#define IRAM_READY		0x80000000 /* ready to use */
+
+typedef struct fm_soft_parser {
+	u8	res[4*1024];
+} fm_soft_parser_t;
+
+typedef struct fm_dtesc {
+	u8	res[4*1024];
+} fm_dtsec_t;
+
+typedef struct fm_mdio {
+	u8	res0[0x120];
+	u32	miimcfg;	/* MII management configuration reg */
+	u32	miimcom;	/* MII management command reg */
+	u32	miimadd;	/* MII management address reg */
+	u32	miimcon;	/* MII management control reg */
+	u32	miimstat;	/* MII management status reg  */
+	u32	miimind;	/* MII management indication reg */
+	u8	res1[0x1000 - 0x138];
+} fm_mdio_t;
+
+typedef struct fm_10gec {
+	u8	res[4*1024];
+} fm_10gec_t;
+
+typedef struct fm_10gec_mdio {
+	u8	res[4*1024];
+} fm_10gec_mdio_t;
+
+typedef struct fm_memac {
+	u8	res[4*1024];
+} fm_memac_t;
+
+typedef struct fm_memac_mdio {
+	u8	res[4*1024];
+} fm_memac_mdio_t;
+
+typedef struct fm_1588 {
+	u8	res[4*1024];
+} fm_1588_t;
+
+typedef struct ccsr_fman {
+	u8			muram[0x80000];
+	fm_bmi_common_t		fm_bmi_common;
+	fm_qmi_common_t		fm_qmi_common;
+	u8			res0[2048];
+	struct {
+		fm_bmi_t	fm_bmi;
+		fm_qmi_t	fm_qmi;
+		fm_parser_t	fm_parser;
+		u8		res[1024];
+	} port[63];
+	fm_policer_t		fm_policer;
+	fm_keygen_t		fm_keygen;
+	fm_dma_t		fm_dma;
+	fm_fpm_t		fm_fpm;
+	fm_imem_t		fm_imem;
+	u8			res1[8*1024];
+	fm_soft_parser_t	fm_soft_parser;
+	u8			res2[96*1024];
+#ifdef CONFIG_SYS_FMAN_V3
+	struct {
+		fm_memac_t		fm_memac;
+		fm_memac_mdio_t		fm_memac_mdio;
+	} memac[10];
+	u8			res4[32*1024];
+	fm_memac_mdio_t		fm_dedicated_mdio[2];
+#else
+	struct {
+		fm_dtsec_t	fm_dtesc;
+		fm_mdio_t	fm_mdio;
+	} mac_1g[8];		/* support up to 8 1g controllers */
+	struct {
+		fm_10gec_t		fm_10gec;
+		fm_10gec_mdio_t		fm_10gec_mdio;
+	} mac_10g[1];
+	u8			res4[48*1024];
+#endif
+	fm_1588_t		fm_1588;
+	u8			res5[4*1024];
+} ccsr_fman_t;
+
+#endif /*__FSL_FMAN_H__*/
diff --git a/include/fsl_tgec.h b/include/fsl_tgec.h
new file mode 100644
index 0000000..92fb777
--- /dev/null
+++ b/include/fsl_tgec.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *	Dave Liu <daveliu@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __TGEC_H__
+#define __TGEC_H__
+
+#include <phy.h>
+
+struct tgec {
+	/* 10GEC general control and status registers */
+	u32	tgec_id;	/* Controller ID register */
+	u32	res0;
+	u32	command_config;	/* Control and configuration register */
+	u32	mac_addr_0;	/* Lower 32 bits of 48-bit MAC address */
+	u32	mac_addr_1;	/* Upper 16 bits of 48-bit MAC address */
+	u32	maxfrm;		/* Maximum frame length register */
+	u32	pause_quant;	/* Pause quanta register */
+	u32	res1[4];
+	u32	hashtable_ctrl;	/* Hash table control register */
+	u32	res2[4];
+	u32	status;		/* MAC status register */
+	u32	tx_ipg_length;	/* Transmitter inter-packet-gap register */
+	u32	mac_addr_2;	/* Lower 32 bits of the 2nd 48-bit MAC addr */
+	u32	mac_addr_3;	/* Upper 16 bits of the 2nd 48-bit MAC addr */
+	u32	res3[4];
+	u32	imask;		/* Interrupt mask register */
+	u32	ievent;		/* Interrupt event register */
+	u32	res4[6];
+	/* 10GEC statistics counter registers */
+	u32	tx_frame_u;	/* Tx frame counter upper */
+	u32	tx_frame_l;	/* Tx frame counter lower */
+	u32	rx_frame_u;	/* Rx frame counter upper */
+	u32	rx_frame_l;	/* Rx frame counter lower */
+	u32	rx_frame_crc_err_u; /* Rx frame check sequence error upper */
+	u32	rx_frame_crc_err_l; /* Rx frame check sequence error lower */
+	u32	rx_align_err_u;	/* Rx alignment error upper */
+	u32	rx_align_err_l;	/* Rx alignment error lower */
+	u32	tx_pause_frame_u; /* Tx valid pause frame upper */
+	u32	tx_pause_frame_l; /* Tx valid pause frame lower */
+	u32	rx_pause_frame_u; /* Rx valid pause frame upper */
+	u32	rx_pause_frame_l; /* Rx valid pause frame upper */
+	u32	rx_long_err_u;	/* Rx too long frame error upper */
+	u32	rx_long_err_l;	/* Rx too long frame error lower */
+	u32	rx_frame_err_u;	/* Rx frame length error upper */
+	u32	rx_frame_err_l;	/* Rx frame length error lower */
+	u32	tx_vlan_u;	/* Tx VLAN frame upper */
+	u32	tx_vlan_l;	/* Tx VLAN frame lower */
+	u32	rx_vlan_u;	/* Rx VLAN frame upper */
+	u32	rx_vlan_l;	/* Rx VLAN frame lower */
+	u32	tx_oct_u;	/* Tx octets upper */
+	u32	tx_oct_l;	/* Tx octets lower */
+	u32	rx_oct_u;	/* Rx octets upper */
+	u32	rx_oct_l;	/* Rx octets lower */
+	u32	rx_uni_u;	/* Rx unicast frame upper */
+	u32	rx_uni_l;	/* Rx unicast frame lower */
+	u32	rx_multi_u;	/* Rx multicast frame upper */
+	u32	rx_multi_l;	/* Rx multicast frame lower */
+	u32	rx_brd_u;	/* Rx broadcast frame upper */
+	u32	rx_brd_l;	/* Rx broadcast frame lower */
+	u32	tx_frame_err_u;	/* Tx frame error upper */
+	u32	tx_frame_err_l;	/* Tx frame error lower */
+	u32	tx_uni_u;	/* Tx unicast frame upper */
+	u32	tx_uni_l;	/* Tx unicast frame lower */
+	u32	tx_multi_u;	/* Tx multicast frame upper */
+	u32	tx_multi_l;	/* Tx multicast frame lower */
+	u32	tx_brd_u;	/* Tx broadcast frame upper */
+	u32	tx_brd_l;	/* Tx broadcast frame lower */
+	u32	rx_drop_u;	/* Rx dropped packets upper */
+	u32	rx_drop_l;	/* Rx dropped packets lower */
+	u32	rx_eoct_u;	/* Rx ethernet octets upper */
+	u32	rx_eoct_l;	/* Rx ethernet octets lower */
+	u32	rx_pkt_u;	/* Rx packets upper */
+	u32	rx_pkt_l;	/* Rx packets lower */
+	u32	tx_undsz_u;	/* Undersized packet upper */
+	u32	tx_undsz_l;	/* Undersized packet lower */
+	u32	rx_64_u;	/* Rx 64 oct packet upper */
+	u32	rx_64_l;	/* Rx 64 oct packet lower */
+	u32	rx_127_u;	/* Rx 65 to 127 oct packet upper */
+	u32	rx_127_l;	/* Rx 65 to 127 oct packet lower */
+	u32	rx_255_u;	/* Rx 128 to 255 oct packet upper */
+	u32	rx_255_l;	/* Rx 128 to 255 oct packet lower */
+	u32	rx_511_u;	/* Rx 256 to 511 oct packet upper */
+	u32	rx_511_l;	/* Rx 256 to 511 oct packet lower */
+	u32	rx_1023_u;	/* Rx 512 to 1023 oct packet upper */
+	u32	rx_1023_l;	/* Rx 512 to 1023 oct packet lower */
+	u32	rx_1518_u;	/* Rx 1024 to 1518 oct packet upper */
+	u32	rx_1518_l;	/* Rx 1024 to 1518 oct packet lower */
+	u32	rx_1519_u;	/* Rx 1519 to max oct packet upper */
+	u32	rx_1519_l;	/* Rx 1519 to max oct packet lower */
+	u32	tx_oversz_u;	/* oversized packet upper */
+	u32	tx_oversz_l;	/* oversized packet lower */
+	u32	tx_jabber_u;	/* Jabber packet upper */
+	u32	tx_jabber_l;	/* Jabber packet lower */
+	u32	tx_frag_u;	/* Fragment packet upper */
+	u32	tx_frag_l;	/* Fragment packet lower */
+	u32	rx_err_u;	/* Rx frame error upper */
+	u32	rx_err_l;	/* Rx frame error lower */
+	u32	res5[0x39a];
+};
+
+/* EC10G_ID - 10-gigabit ethernet MAC controller ID */
+#define EC10G_ID_VER_MASK	0x0000ff00
+#define EC10G_ID_VER_SHIFT	8
+#define EC10G_ID_REV_MASK	0x000000ff
+
+/* COMMAND_CONFIG - command and configuration register */
+#define TGEC_CMD_CFG_EN_TIMESTAMP	0x00100000 /* enable IEEE1588 */
+#define TGEC_CMD_CFG_TX_ADDR_INS_SEL	0x00080000 /* Tx mac addr w/ second */
+#define TGEC_CMD_CFG_NO_LEN_CHK		0x00020000 /* payload len chk disable */
+#define TGEC_CMD_CFG_SEND_IDLE		0x00010000 /* send XGMII idle seqs */
+#define TGEC_CMD_CFG_RX_ER_DISC		0x00004000 /* Rx err frm discard enb */
+#define TGEC_CMD_CFG_CMD_FRM_EN		0x00002000 /* CMD frame RX enable */
+#define TGEC_CMD_CFG_STAT_CLR		0x00001000 /* clear stats */
+#define TGEC_CMD_CFG_TX_ADDR_INS	0x00000200 /* overwrite src MAC addr */
+#define TGEC_CMD_CFG_PAUSE_IGNORE	0x00000100 /* ignore pause frames */
+#define TGEC_CMD_CFG_PAUSE_FWD		0x00000080 /* fwd pause frames */
+#define TGEC_CMD_CFG_CRC_FWD		0x00000040 /* fwd Rx CRC frames */
+#define TGEC_CMD_CFG_PAD_EN		0x00000020 /* MAC remove Rx padding */
+#define TGEC_CMD_CFG_PROM_EN		0x00000010 /* promiscuous mode enable */
+#define TGEC_CMD_CFG_WAN_MODE		0x00000008 /* WAN mode enable */
+#define TGEC_CMD_CFG_RX_EN		0x00000002 /* MAC Rx path enable */
+#define TGEC_CMD_CFG_TX_EN		0x00000001 /* MAC Tx path enable */
+#define TGEC_CMD_CFG_RXTX_EN	(TGEC_CMD_CFG_RX_EN | TGEC_CMD_CFG_TX_EN)
+
+/* HASHTABLE_CTRL - Hashtable control register */
+#define HASHTABLE_CTRL_MCAST_EN	0x00000200 /* enable mulitcast Rx hash */
+#define HASHTABLE_CTRL_ADDR_MASK	0x000001ff
+
+/* TX_IPG_LENGTH - Transmit inter-packet gap length register */
+#define TX_IPG_LENGTH_IPG_LEN_MASK	0x000003ff
+
+/* IMASK - interrupt mask register */
+#define IMASK_MDIO_SCAN_EVENT	0x00010000 /* MDIO scan event mask */
+#define IMASK_MDIO_CMD_CMPL	0x00008000 /* MDIO cmd completion mask */
+#define IMASK_REM_FAULT		0x00004000 /* remote fault mask */
+#define IMASK_LOC_FAULT		0x00002000 /* local fault mask */
+#define IMASK_TX_ECC_ER		0x00001000 /* Tx frame ECC error mask */
+#define IMASK_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow mask */
+#define IMASK_TX_ER		0x00000200 /* Tx frame error mask */
+#define IMASK_RX_FIFO_OVFL	0x00000100 /* Rx FIFO overflow mask */
+#define IMASK_RX_ECC_ER		0x00000080 /* Rx frame ECC error mask */
+#define IMASK_RX_JAB_FRM	0x00000040 /* Rx jabber frame mask */
+#define IMASK_RX_OVRSZ_FRM	0x00000020 /* Rx oversized frame mask */
+#define IMASK_RX_RUNT_FRM	0x00000010 /* Rx runt frame mask */
+#define IMASK_RX_FRAG_FRM	0x00000008 /* Rx fragment frame mask */
+#define IMASK_RX_LEN_ER		0x00000004 /* Rx payload length error mask */
+#define IMASK_RX_CRC_ER		0x00000002 /* Rx CRC error mask */
+#define IMASK_RX_ALIGN_ER	0x00000001 /* Rx alignment error mask */
+
+#define IMASK_MASK_ALL		0x00000000
+
+/* IEVENT - interrupt event register */
+#define IEVENT_MDIO_SCAN_EVENT	0x00010000 /* MDIO scan event */
+#define IEVENT_MDIO_CMD_CMPL	0x00008000 /* MDIO cmd completion */
+#define IEVENT_REM_FAULT	0x00004000 /* remote fault */
+#define IEVENT_LOC_FAULT	0x00002000 /* local fault */
+#define IEVENT_TX_ECC_ER	0x00001000 /* Tx frame ECC error */
+#define IEVENT_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow */
+#define IEVENT_TX_ER		0x00000200 /* Tx frame error */
+#define IEVENT_RX_FIFO_OVFL	0x00000100 /* Rx FIFO overflow */
+#define IEVENT_RX_ECC_ER	0x00000080 /* Rx frame ECC error */
+#define IEVENT_RX_JAB_FRM	0x00000040 /* Rx jabber frame */
+#define IEVENT_RX_OVRSZ_FRM	0x00000020 /* Rx oversized frame */
+#define IEVENT_RX_RUNT_FRM	0x00000010 /* Rx runt frame */
+#define IEVENT_RX_FRAG_FRM	0x00000008 /* Rx fragment frame */
+#define IEVENT_RX_LEN_ER	0x00000004 /* Rx payload length error */
+#define IEVENT_RX_CRC_ER	0x00000002 /* Rx CRC error */
+#define IEVENT_RX_ALIGN_ER	0x00000001 /* Rx alignment error */
+
+#define IEVENT_CLEAR_ALL	0xffffffff
+
+struct tgec_mdio_controller {
+	u32	res0[0xc];
+	u32	mdio_stat;	/* MDIO configuration and status */
+	u32	mdio_ctl;	/* MDIO control */
+	u32	mdio_data;	/* MDIO data */
+	u32	mdio_addr;	/* MDIO address */
+};
+
+#define MDIO_STAT_CLKDIV(x)	(((x>>1) & 0xff) << 8)
+#define MDIO_STAT_BSY		(1 << 0)
+#define MDIO_STAT_RD_ER		(1 << 1)
+#define MDIO_CTL_DEV_ADDR(x)	(x & 0x1f)
+#define MDIO_CTL_PORT_ADDR(x)	((x & 0x1f) << 5)
+#define MDIO_CTL_PRE_DIS	(1 << 10)
+#define MDIO_CTL_SCAN_EN	(1 << 11)
+#define MDIO_CTL_POST_INC	(1 << 14)
+#define MDIO_CTL_READ		(1 << 15)
+
+#define MDIO_DATA(x)		(x & 0xffff)
+#define MDIO_DATA_BSY		(1 << 31)
+
+struct fsl_enet_mac;
+
+void init_tgec(struct fsl_enet_mac *mac, void *base, void *phyregs,
+		int max_rx_len);
+
+#endif
-- 
2.1.0.27.g96db324

^ permalink raw reply related	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 06/16] net/fm: Add QSGMII PCS init
  2015-09-17  7:06 [U-Boot] [Patch v2 04/16] net/fm: bug fix when CONFIG_PHYLIB not defined Gong Qianyu
  2015-09-17  7:06 ` [U-Boot] [Patch v2 05/16] net: Move some header files to include/ Gong Qianyu
@ 2015-09-17  7:06 ` Gong Qianyu
  2015-09-17  7:06 ` [U-Boot] [Patch v2 07/16] net/fm: fix MDIO controller base on FMAN2 Gong Qianyu
                   ` (9 subsequent siblings)
  11 siblings, 0 replies; 33+ messages in thread
From: Gong Qianyu @ 2015-09-17  7:06 UTC (permalink / raw)
  To: u-boot

From: Shaohui Xie <Shaohui.Xie@freescale.com>

QSGMII PCS needed to be programmed same as SGMII PCS, and there are
four ports in QSGMII PCS, port 0, 1, 2, 3, all the four ports shared
port 0's MDIO controller, so when programming port 0, we continue to
program other three ports.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
---
 drivers/net/fm/eth.c | 22 +++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index a768a90..12eb9b8 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -41,28 +41,39 @@ static void dtsec_configure_serdes(struct fm_eth *priv)
 	bus.priv = priv->mac->phyregs;
 	bool sgmii_2500 = (priv->enet_if ==
 			PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
+	int i = 0;
+
+qsgmii_loop:
+	if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) &&
+	    ((priv->phyaddr % 4) != 0))
+		return;
 
 	/* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
 	value = PHY_SGMII_IF_MODE_SGMII;
 	if (!sgmii_2500)
 		value |= PHY_SGMII_IF_MODE_AN;
 
-	memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
+	memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value);
 
 	/* Dev ability according to SGMII specification */
 	value = PHY_SGMII_DEV_ABILITY_SGMII;
-	memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value);
+	memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value);
 
 	/* Adjust link timer for SGMII  -
 	1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
-	memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x3);
-	memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40);
+	memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x3);
+	memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xd40);
 
 	/* Restart AN */
 	value = PHY_SGMII_CR_DEF_VAL;
 	if (!sgmii_2500)
 		value |= PHY_SGMII_CR_RESET_AN;
-	memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
+	memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value);
+
+	if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
+		i++;
+		goto qsgmii_loop;
+	}
 #else
 	struct dtsec *regs = priv->mac->base;
 	struct tsec_mii_mng *phyregs = priv->mac->phyregs;
@@ -91,6 +102,7 @@ static void dtsec_init_phy(struct eth_device *dev)
 #endif
 
 	if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
+	    fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
 	    fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
 		dtsec_configure_serdes(fm_eth);
 }
-- 
2.1.0.27.g96db324

^ permalink raw reply related	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 07/16] net/fm: fix MDIO controller base on FMAN2
  2015-09-17  7:06 [U-Boot] [Patch v2 04/16] net/fm: bug fix when CONFIG_PHYLIB not defined Gong Qianyu
  2015-09-17  7:06 ` [U-Boot] [Patch v2 05/16] net: Move some header files to include/ Gong Qianyu
  2015-09-17  7:06 ` [U-Boot] [Patch v2 06/16] net/fm: Add QSGMII PCS init Gong Qianyu
@ 2015-09-17  7:06 ` Gong Qianyu
  2015-09-17 18:04   ` Scott Wood
  2015-09-17  7:06 ` [U-Boot] [Patch v2 08/16] net/fm: fix compile warnings for 64-bit platform Gong Qianyu
                   ` (8 subsequent siblings)
  11 siblings, 1 reply; 33+ messages in thread
From: Gong Qianyu @ 2015-09-17  7:06 UTC (permalink / raw)
  To: u-boot

From: Shaohui Xie <Shaohui.Xie@freescale.com>

MDIO controller base on FMAN2 was defined as CONFIG_SYS_FSL_FM2_ADDR
plus offset, but CONFIG_SYS_FSL_FM2_ADDR only defined when there are two
FMANs, so we should only define MDIO controller base on FMAN2 when there
is FMAN2.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
---
 include/fm_eth.h | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/include/fm_eth.h b/include/fm_eth.h
index 3e1b9f4..d43f801 100644
--- a/include/fm_eth.h
+++ b/include/fm_eth.h
@@ -45,8 +45,10 @@ enum fm_eth_type {
 #ifdef CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
 #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
+#if (CONFIG_SYS_NUM_FMAN == 2)
 #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)
 #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM2_ADDR + 0xfd000)
+#endif
 #else
 #define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR	(CONFIG_SYS_FSL_FM1_ADDR + 0xe1120)
 #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM1_ADDR + 0xf1000)
@@ -89,6 +91,7 @@ enum fm_eth_type {
 				 offsetof(struct ccsr_fman, memac[n-1]),\
 }
 #else
+#if (CONFIG_SYS_NUM_FMAN == 2)
 #define FM_TGEC_INFO_INITIALIZER(idx, n) \
 {									\
 	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR)	\
@@ -101,6 +104,20 @@ enum fm_eth_type {
 	.compat_offset	= CONFIG_SYS_FSL_FM##idx##_OFFSET +		\
 				offsetof(struct ccsr_fman, memac[n-1+8]),\
 }
+#else
+#define FM_TGEC_INFO_INITIALIZER(idx, n) \
+{									\
+	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)	\
+	.index		= idx,						\
+	.num		= n - 1,					\
+	.type		= FM_ETH_10G_E,					\
+	.port		= FM##idx##_10GEC##n,				\
+	.rx_port_id	= RX_PORT_10G_BASE + n - 1,			\
+	.tx_port_id	= TX_PORT_10G_BASE + n - 1,			\
+	.compat_offset	= CONFIG_SYS_FSL_FM##idx##_OFFSET +		\
+				offsetof(struct ccsr_fman, memac[n-1+8]),\
+}
+#endif
 #endif
 
 #if (CONFIG_SYS_NUM_FM1_10GEC >= 3)
-- 
2.1.0.27.g96db324

^ permalink raw reply related	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 08/16] net/fm: fix compile warnings for 64-bit platform
  2015-09-17  7:06 [U-Boot] [Patch v2 04/16] net/fm: bug fix when CONFIG_PHYLIB not defined Gong Qianyu
                   ` (2 preceding siblings ...)
  2015-09-17  7:06 ` [U-Boot] [Patch v2 07/16] net/fm: fix MDIO controller base on FMAN2 Gong Qianyu
@ 2015-09-17  7:06 ` Gong Qianyu
  2015-09-17 18:13   ` Scott Wood
  2015-09-17  7:06 ` [U-Boot] [Patch v2 09/16] ARMv8/FSL_LSCH2: Add FSL_LSCH2 SoC Gong Qianyu
                   ` (7 subsequent siblings)
  11 siblings, 1 reply; 33+ messages in thread
From: Gong Qianyu @ 2015-09-17  7:06 UTC (permalink / raw)
  To: u-boot

This patch fixes such compile warnings:

drivers/net/fm/eth.c: In function 'fm_eth_recv':
drivers/net/fm/eth.c:549:11: warning: cast to pointer from integer of
different size [-Wint-to-pointer-cast]
	data = (u8 *)in_be32(&rxbd->buf_ptr_lo);
drivers/net/fm/fm.c: In function 'fm_muram_alloc':
drivers/net/fm/fm.c:52:9: warning: cast to pointer from integer of
different size [-Wint-to-pointer-cast]
	memset((void *)ret, 0, size);
drivers/net/fm/fm.c: In function 'fm_init_muram':
drivers/net/fm/fm.c:59:13: warning: cast from pointer to integer of
different size [-Wpointer-to-int-cast]
	u32 base = (u32)reg;

Just make the cast explicit for them.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
---
 drivers/net/fm/eth.c | 31 ++++++++++++++++---------------
 drivers/net/fm/fm.c  |  4 ++--
 2 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 12eb9b8..6ef0afb 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -120,12 +120,12 @@ static int tgec_is_fibre(struct eth_device *dev)
 
 static u16 muram_readw(u16 *addr)
 {
-	u32 base = (u32)addr & ~0x3;
+	ulong base = (ulong)addr & ~0x3;
 	u32 val32 = in_be32((u32 *)base);
 	int byte_pos;
 	u16 ret;
 
-	byte_pos = (u32)addr & 0x3;
+	byte_pos = (ulong)addr & 0x3;
 	if (byte_pos)
 		ret = (u16)(val32 & 0x0000ffff);
 	else
@@ -136,12 +136,12 @@ static u16 muram_readw(u16 *addr)
 
 static void muram_writew(u16 *addr, u16 val)
 {
-	u32 base = (u32)addr & ~0x3;
+	ulong base = (ulong)addr & ~0x3;
 	u32 org32 = in_be32((u32 *)base);
 	u32 val32;
 	int byte_pos;
 
-	byte_pos = (u32)addr & 0x3;
+	byte_pos = (ulong)addr & 0x3;
 	if (byte_pos)
 		val32 = (org32 & 0xffff0000) | val;
 	else
@@ -217,12 +217,12 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
 	int i;
 
 	/* alloc global parameter ram at MURAM */
-	pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
-		FM_PRAM_SIZE, FM_PRAM_ALIGN);
+	pram = (struct fm_port_global_pram *)(ulong)fm_muram_alloc(
+			fm_eth->fm_index, FM_PRAM_SIZE, FM_PRAM_ALIGN);
 	fm_eth->rx_pram = pram;
 
 	/* parameter page offset to MURAM */
-	pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
+	pram_page_offset = (u32)(ulong)pram - fm_muram_base(fm_eth->fm_index);
 
 	/* enable global mode- snooping data buffers and BDs */
 	out_be32(&pram->mode, PRAM_MODE_GLOBAL);
@@ -258,7 +258,8 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
 		muram_writew(&rxbd->status, RxBD_EMPTY);
 		muram_writew(&rxbd->len, 0);
 		muram_writew(&rxbd->buf_ptr_hi, 0);
-		out_be32(&rxbd->buf_ptr_lo, (u32)rx_buf_pool + i * MAX_RXBUF_LEN);
+		out_be32(&rxbd->buf_ptr_lo, (u32)(ulong)rx_buf_pool +
+							i * MAX_RXBUF_LEN);
 		rxbd++;
 	}
 
@@ -266,7 +267,7 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
 	rxqd = &pram->rxqd;
 	muram_writew(&rxqd->gen, 0);
 	muram_writew(&rxqd->bd_ring_base_hi, 0);
-	out_be32(&rxqd->bd_ring_base_lo, (u32)rx_bd_ring_base);
+	out_be32(&rxqd->bd_ring_base_lo, (u32)(ulong)rx_bd_ring_base);
 	muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
 			* RX_BD_RING_SIZE);
 	muram_writew(&rxqd->offset_in, 0);
@@ -289,12 +290,12 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
 	int i;
 
 	/* alloc global parameter ram at MURAM */
-	pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
-		FM_PRAM_SIZE, FM_PRAM_ALIGN);
+	pram = (struct fm_port_global_pram *)(ulong)fm_muram_alloc(
+			fm_eth->fm_index, FM_PRAM_SIZE, FM_PRAM_ALIGN);
 	fm_eth->tx_pram = pram;
 
 	/* parameter page offset to MURAM */
-	pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
+	pram_page_offset = (u32)(ulong)pram - fm_muram_base(fm_eth->fm_index);
 
 	/* enable global mode- snooping data buffers and BDs */
 	out_be32(&pram->mode, PRAM_MODE_GLOBAL);
@@ -326,7 +327,7 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
 	/* set the Tx queue decriptor */
 	txqd = &pram->txqd;
 	muram_writew(&txqd->bd_ring_base_hi, 0);
-	out_be32(&txqd->bd_ring_base_lo, (u32)tx_bd_ring_base);
+	out_be32(&txqd->bd_ring_base_lo, (u32)(ulong)tx_bd_ring_base);
 	muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
 			* TX_BD_RING_SIZE);
 	muram_writew(&txqd->offset_in, 0);
@@ -494,7 +495,7 @@ static int fm_eth_send(struct eth_device *dev, void *buf, int len)
 	}
 	/* setup TxBD */
 	muram_writew(&txbd->buf_ptr_hi, 0);
-	out_be32(&txbd->buf_ptr_lo, (u32)buf);
+	out_be32(&txbd->buf_ptr_lo, (u32)(ulong)buf);
 	muram_writew(&txbd->len, len);
 	mb();
 	muram_writew(&txbd->status, TxBD_READY | TxBD_LAST);
@@ -546,7 +547,7 @@ static int fm_eth_recv(struct eth_device *dev)
 
 	while (!(status & RxBD_EMPTY)) {
 		if (!(status & RxBD_ERROR)) {
-			data = (u8 *)in_be32(&rxbd->buf_ptr_lo);
+			data = (u8 *)(ulong)in_be32(&rxbd->buf_ptr_lo);
 			len = muram_readw(&rxbd->len);
 			net_process_received_packet(data, len);
 		} else {
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index eb0eb3d..33332d6 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -49,14 +49,14 @@ u32 fm_muram_alloc(int fm_idx, u32 size, u32 align)
 
 	ret = muram[fm_idx].alloc;
 	muram[fm_idx].alloc += size;
-	memset((void *)ret, 0, size);
+	memset((void *)(ulong)ret, 0, size);
 
 	return ret;
 }
 
 static void fm_init_muram(int fm_idx, void *reg)
 {
-	u32 base = (u32)reg;
+	u32 base = (u32)(ulong)reg;
 
 	muram[fm_idx].base = base;
 	muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE;
-- 
2.1.0.27.g96db324

^ permalink raw reply related	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 09/16] ARMv8/FSL_LSCH2: Add FSL_LSCH2 SoC
  2015-09-17  7:06 [U-Boot] [Patch v2 04/16] net/fm: bug fix when CONFIG_PHYLIB not defined Gong Qianyu
                   ` (3 preceding siblings ...)
  2015-09-17  7:06 ` [U-Boot] [Patch v2 08/16] net/fm: fix compile warnings for 64-bit platform Gong Qianyu
@ 2015-09-17  7:06 ` Gong Qianyu
  2015-09-21 17:27   ` York Sun
  2015-09-17  7:06 ` [U-Boot] [Patch v2 10/16] ARMv8/ls1043ardb: Add LS1043ARDB board support Gong Qianyu
                   ` (6 subsequent siblings)
  11 siblings, 1 reply; 33+ messages in thread
From: Gong Qianyu @ 2015-09-17  7:06 UTC (permalink / raw)
  To: u-boot

From: Mingkai Hu <Mingkai.Hu@freescale.com>

Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
ARMv8 cores and 2rd generation of Chassis.

Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
---
V2:
remove FSL_LS102xA_DEVDISR3_PCIE from immap_lsch2.h

 arch/arm/cpu/armv8/Makefile                       |   1 +
 arch/arm/cpu/armv8/fsl-lsch2/Makefile             |  12 +
 arch/arm/cpu/armv8/fsl-lsch2/README               |  10 +
 arch/arm/cpu/armv8/fsl-lsch2/cpu.c                | 414 ++++++++++++++++++
 arch/arm/cpu/armv8/fsl-lsch2/fdt.c                |  13 +
 arch/arm/cpu/armv8/fsl-lsch2/fsl_lsch2_serdes.c   | 116 +++++
 arch/arm/cpu/armv8/fsl-lsch2/lowlevel.S           | 122 ++++++
 arch/arm/cpu/armv8/fsl-lsch2/ls1043a_serdes.c     |  86 ++++
 arch/arm/cpu/armv8/fsl-lsch2/soc.c                |  36 ++
 arch/arm/cpu/armv8/fsl-lsch2/speed.c              | 137 ++++++
 arch/arm/cpu/armv8/fsl-lsch2/speed.h              |   7 +
 arch/arm/include/asm/arch-fsl-lsch2/clock.h       |  24 ++
 arch/arm/include/asm/arch-fsl-lsch2/config.h      | 150 +++++++
 arch/arm/include/asm/arch-fsl-lsch2/fsl_serdes.h  | 105 +++++
 arch/arm/include/asm/arch-fsl-lsch2/gpio.h        |   9 +
 arch/arm/include/asm/arch-fsl-lsch2/immap_lsch2.h | 496 ++++++++++++++++++++++
 arch/arm/include/asm/arch-fsl-lsch2/imx-regs.h    |  52 +++
 arch/arm/include/asm/arch-fsl-lsch2/mmu.h         |  10 +
 arch/arm/include/asm/arch-fsl-lsch2/ns_access.h   | 158 +++++++
 arch/arm/include/asm/arch-fsl-lsch2/soc.h         |   7 +
 arch/arm/include/asm/arch-fsl-lsch2/spl.h         |  20 +
 arch/arm/include/asm/armv8/mmu.h                  |   1 +
 arch/arm/include/asm/config.h                     |   3 +
 include/common.h                                  |   3 +
 24 files changed, 1992 insertions(+)

diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index adb11b3..eee8344 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -15,6 +15,7 @@ obj-y	+= cache.o
 obj-y	+= tlb.o
 obj-y	+= transition.o
 
+obj-$(CONFIG_FSL_LSCH2) += fsl-lsch2/
 obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/
 obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
 obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/Makefile b/arch/arm/cpu/armv8/fsl-lsch2/Makefile
new file mode 100644
index 0000000..2280ebf
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch2/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2015, Freescale Semiconductor
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += cpu.o
+obj-y += soc.o
+obj-y += lowlevel.o
+obj-y += speed.o
+obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o ls1043a_serdes.o
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/README b/arch/arm/cpu/armv8/fsl-lsch2/README
new file mode 100644
index 0000000..a6ef830
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch2/README
@@ -0,0 +1,10 @@
+#
+# Copyright 2015 Freescale Semiconductor
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+Freescale LayerScape with Chassis Generation 2
+
+This architecture supports Freescale ARMv8 SoCs with Chassis generation 2,
+for example LS1043A.
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/cpu.c b/arch/arm/cpu/armv8/fsl-lsch2/cpu.c
new file mode 100644
index 0000000..1155723
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch2/cpu.c
@@ -0,0 +1,414 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+#include <asm/arch-fsl-lsch2/immap_lsch2.h>
+#include <asm/arch/fsl_serdes.h>
+#include "speed.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+/*
+ * To start MMU before DDR is available, we create MMU table in SRAM.
+ * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
+ * levels of translation tables here to cover 40-bit address space.
+ * We use 4KB granule size, with 40 bits physical address, T0SZ=24
+ * Level 0 IA[39], table address @0
+ * Level 1 IA[31:30], table address @01000, 0x2000
+ * Level 2 IA[29:21], table address @0x3000
+ */
+
+#define SECTION_SHIFT_L0	39UL
+#define SECTION_SHIFT_L1	30UL
+#define SECTION_SHIFT_L2	21UL
+#define BLOCK_SIZE_L0	0x8000000000UL
+#define BLOCK_SIZE_L1	(1 << SECTION_SHIFT_L1)
+#define BLOCK_SIZE_L2	(1 << SECTION_SHIFT_L2)
+#define CONFIG_SYS_IFC_BASE	0x60000000UL
+#define CONFIG_SYS_IFC_SIZE	0x20000000UL
+#define CONFIG_SYS_IFC_BASE2	0x620000000UL
+#define CONFIG_SYS_IFC_SIZE2	0x0e0000000UL
+#define TCR_EL2_PS_40BIT	(2 << 16)
+#define LSCH2_VA_BITS		(40)
+#define LSCH2_TCR	(TCR_TG0_4K		| \
+			TCR_EL2_PS_40BIT	| \
+			TCR_SHARED_NON		| \
+			TCR_ORGN_NC		| \
+			TCR_IRGN_NC		| \
+			TCR_T0SZ(LSCH2_VA_BITS))
+#define LSCH2_TCR_FINAL	(TCR_TG0_4K		| \
+			TCR_EL2_PS_40BIT	| \
+			TCR_SHARED_OUTER	| \
+			TCR_ORGN_WBWA		| \
+			TCR_IRGN_WBWA		| \
+			TCR_T0SZ(LSCH2_VA_BITS))
+
+/*
+ * Final MMU
+ * Let's start from the same layout as early MMU and modify as needed.
+ * IFC regions will be cache-inhibit.
+ */
+#define FINAL_QBMAN_CACHED_MEM	0x818000000UL
+#define FINAL_QBMAN_CACHED_SIZE	0x4000000
+
+static inline void early_mmu_setup(void)
+{
+	int el;
+	u64 i;
+	u64 section_l1t0, section_l1t1, section_l2;
+	u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE;
+	u64 *level1_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000);
+	u64 *level1_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000);
+	u64 *level2_table = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000);
+
+
+	level0_table[0] =
+		(u64)level1_table_0 | PMD_TYPE_TABLE;
+	level0_table[1] =
+		(u64)level1_table_1 | PMD_TYPE_TABLE;
+
+	/*
+	 * set level 1 table 0 to cache_inhibit, covering 0 to 512GB
+	 * set level 1 table 1 to cache enabled, covering 512GB to 1TB
+	 * set level 2 table to cache-inhibit, covering 0 to 1GB
+	 */
+	section_l1t0 = 0;
+	section_l1t1 = BLOCK_SIZE_L0;
+	section_l2 = 0;
+	for (i = 0; i < 512; i++) {
+		set_pgtable_section(level1_table_0, i, section_l1t0,
+				    MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE);
+		set_pgtable_section(level1_table_1, i, section_l1t1,
+				    MT_NORMAL, PMD_SECT_NON_SHARE);
+		set_pgtable_section(level2_table, i, section_l2,
+				    MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE);
+		section_l1t0 += BLOCK_SIZE_L1;
+		section_l1t1 += BLOCK_SIZE_L1;
+		section_l2 += BLOCK_SIZE_L2;
+	}
+
+	level1_table_0[0] =
+		(u64)level2_table | PMD_TYPE_TABLE;
+	level1_table_0[1] =
+		0x40000000 | PMD_SECT_AF | PMD_TYPE_SECT |
+		PMD_ATTRINDX(MT_DEVICE_NGNRNE);
+	level1_table_0[2] =
+		0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT |
+		PMD_ATTRINDX(MT_NORMAL);
+	level1_table_0[3] =
+		0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT |
+		PMD_ATTRINDX(MT_NORMAL);
+
+	/* Rewrite table to enable cache */
+	set_pgtable_section(level2_table,
+			    CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2,
+			    CONFIG_SYS_FSL_OCRAM_BASE,
+			    MT_NORMAL,
+			    PMD_SECT_NON_SHARE);
+	for (i = CONFIG_SYS_IFC_BASE >> SECTION_SHIFT_L2;
+	     i < (CONFIG_SYS_IFC_BASE + CONFIG_SYS_IFC_SIZE)
+	     >> SECTION_SHIFT_L2; i++) {
+		section_l2 = i << SECTION_SHIFT_L2;
+		set_pgtable_section(level2_table, i,
+				    section_l2, MT_NORMAL,
+				    PMD_SECT_NON_SHARE);
+	}
+
+	el = current_el();
+	set_ttbr_tcr_mair(el, (u64)level0_table, LSCH2_TCR, MEMORY_ATTRIBUTES);
+	set_sctlr(get_sctlr() | CR_M);
+}
+
+static inline void final_mmu_setup(void)
+{
+	int el;
+	u64 i, tbl_base, tbl_limit, section_base;
+	u64 section_l1t0, section_l1t1, section_l2;
+	u64 *level0_table = (u64 *)gd->arch.tlb_addr;
+	u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + 0x1000);
+	u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + 0x2000);
+	u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + 0x3000);
+	u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
+
+
+	level0_table[0] =
+		(u64)level1_table_0 | PMD_TYPE_TABLE;
+	level0_table[1] =
+		(u64)level1_table_1 | PMD_TYPE_TABLE;
+
+	/*
+	 * set level 1 table 0 to cache_inhibit, covering 0 to 512GB
+	 * set level 1 table 1 to cache enabled, covering 512GB to 1TB
+	 * set level 2 table 0 to cache-inhibit, covering 0 to 1GB
+	 */
+	section_l1t0 = 0;
+	section_l1t1 = BLOCK_SIZE_L0 | PMD_SECT_OUTER_SHARE;
+	section_l2 = 0;
+	for (i = 0; i < 512; i++) {
+		set_pgtable_section(level1_table_0, i, section_l1t0,
+				    MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE);
+		set_pgtable_section(level1_table_1, i, section_l1t1,
+				    MT_NORMAL, PMD_SECT_NON_SHARE);
+		set_pgtable_section(level2_table_0, i, section_l2,
+				    MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE);
+		section_l1t0 += BLOCK_SIZE_L1;
+		section_l1t1 += BLOCK_SIZE_L1;
+		section_l2 += BLOCK_SIZE_L2;
+	}
+
+	level1_table_0[0] =
+		(u64)level2_table_0 | PMD_TYPE_TABLE;
+	level1_table_0[2] =
+		0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT |
+		PMD_SECT_OUTER_SHARE | PMD_SECT_NS | PMD_ATTRINDX(MT_NORMAL);
+	level1_table_0[3] =
+		0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT |
+		PMD_SECT_OUTER_SHARE | PMD_SECT_NS | PMD_ATTRINDX(MT_NORMAL);
+
+	/* Rewrite table to enable cache */
+	set_pgtable_section(level2_table_0,
+			    CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2,
+			    CONFIG_SYS_FSL_OCRAM_BASE,
+			    MT_NORMAL,
+			    PMD_SECT_NON_SHARE);
+
+	/*
+	 * Fill in other part of tables if cache is needed
+	 * If finer granularity than 1GB is needed, sub table
+	 * should be created.
+	 */
+	section_base = FINAL_QBMAN_CACHED_MEM & ~(BLOCK_SIZE_L1 - 1);
+	i = section_base >> SECTION_SHIFT_L1;
+	level1_table_0[i] = (u64)level2_table_1 | PMD_TYPE_TABLE;
+	section_l2 = section_base;
+	for (i = 0; i < 512; i++) {
+		set_pgtable_section(level2_table_1, i, section_l2,
+				    MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE);
+		section_l2 += BLOCK_SIZE_L2;
+	}
+	tbl_base = FINAL_QBMAN_CACHED_MEM & (BLOCK_SIZE_L1 - 1);
+	tbl_limit = (FINAL_QBMAN_CACHED_MEM + FINAL_QBMAN_CACHED_SIZE) &
+		    (BLOCK_SIZE_L1 - 1);
+	for (i = tbl_base >> SECTION_SHIFT_L2;
+	     i < tbl_limit >> SECTION_SHIFT_L2; i++) {
+		section_l2 = section_base + (i << SECTION_SHIFT_L2);
+		set_pgtable_section(level2_table_1, i,
+				    section_l2, MT_NORMAL, PMD_SECT_NON_SHARE);
+	}
+
+	/* flush new MMU table */
+	flush_dcache_range(gd->arch.tlb_addr,
+			   gd->arch.tlb_addr +  gd->arch.tlb_size);
+	flush_dcache_all();
+
+	el = current_el();
+	set_ttbr_tcr_mair(el, (u64)level0_table, LSCH2_TCR_FINAL,
+			  MEMORY_ATTRIBUTES);
+
+	/*
+	 * MMU is already enabled, just need to invalidate TLB to load the
+	 * new table. The new table is compatible with the current table, if
+	 * MMU somehow walks through the new table before invalidation TLB,
+	 * it still works. So we don't need to turn off MMU here.
+	 */
+}
+
+int arch_cpu_init(void)
+{
+	icache_enable();
+	__asm_invalidate_dcache_all();
+	__asm_invalidate_tlb_all();
+	early_mmu_setup();
+	set_sctlr(get_sctlr() | CR_C);
+	return 0;
+}
+
+/*
+ * This function is called from lib/board.c.
+ * It recreates MMU table in main memory. MMU and d-cache are enabled earlier.
+ * There is no need to disable d-cache for this operation.
+ */
+void enable_caches(void)
+{
+	final_mmu_setup();
+	__asm_invalidate_tlb_all();
+}
+#endif
+
+
+static inline u32 initiator_type(u32 cluster, int init_id)
+{
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
+	u32 type = in_be32(&gur->tp_ityp[idx]);
+
+	if (type & TP_ITYP_AV)
+		return type;
+
+	return 0;
+}
+
+u32 cpu_mask(void)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	int i = 0, count = 0;
+	u32 cluster, type, mask = 0;
+
+	do {
+		int j;
+		cluster = in_be32(&gur->tp_cluster[i].lower);
+		for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+			type = initiator_type(cluster, j);
+			if (type) {
+				if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
+					mask |= 1 << count;
+				count++;
+			}
+		}
+		i++;
+	} while ((cluster & TP_CLUSTER_EOC_MASK) == 0x0);
+
+	return mask;
+}
+
+/*
+ * Return the number of cores on this SOC.
+ */
+int cpu_numcores(void)
+{
+	return hweight32(cpu_mask());
+}
+
+int fsl_qoriq_core_to_cluster(unsigned int core)
+{
+	struct ccsr_gur __iomem *gur =
+		(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	int i = 0, count = 0;
+	u32 cluster;
+
+	do {
+		int j;
+		cluster = in_be32(&gur->tp_cluster[i].lower);
+		for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+			if (initiator_type(cluster, j)) {
+				if (count == core)
+					return i;
+				count++;
+			}
+		}
+		i++;
+	} while ((cluster & TP_CLUSTER_EOC_MASK) == 0x0);
+
+	return -1;      /* cannot identify the cluster */
+}
+
+u32 fsl_qoriq_core_to_type(unsigned int core)
+{
+	struct ccsr_gur __iomem *gur =
+		(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	int i = 0, count = 0;
+	u32 cluster, type;
+
+	do {
+		int j;
+		cluster = in_be32(&gur->tp_cluster[i].lower);
+		for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+			type = initiator_type(cluster, j);
+			if (type) {
+				if (count == core)
+					return type;
+				count++;
+			}
+		}
+		i++;
+	} while ((cluster & TP_CLUSTER_EOC_MASK) == 0x0);
+
+	return -1;      /* cannot identify the cluster */
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct sys_info sysinfo;
+	char buf[32];
+	unsigned int i, core;
+	u32 type;
+
+	get_sys_info(&sysinfo);
+	puts("Clock Configuration:");
+	for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
+		if (!(i % 3))
+			puts("\n       ");
+		type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
+		printf("CPU%d(%s):%-4s MHz  ", core,
+		       type == TY_ITYP_VER_A7 ? "A7 " :
+		       (type == TY_ITYP_VER_A53 ? "A53" :
+			(type == TY_ITYP_VER_A57 ? "A57" : "   ")),
+		       strmhz(buf, sysinfo.freq_processor[core]));
+	}
+	printf("\n       Bus:      %-4s MHz  ",
+	       strmhz(buf, sysinfo.freq_systembus));
+	printf("DDR:      %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
+	puts("\n");
+
+	/*
+	 * Display the RCW, so that no one gets confused as to what RCW
+	 * we're actually using for this boot.
+	 */
+	puts("Reset Configuration Word (RCW):");
+	for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
+		u32 rcw = in_be32(&gur->rcwsr[i]);
+
+		if ((i % 4) == 0)
+			printf("\n       %08x:", i * 4);
+		printf(" %08x", rcw);
+	}
+	puts("\n");
+
+	return 0;
+}
+#endif
+
+int arch_early_init_r(void)
+{
+#ifdef CONFIG_SYS_HAS_SERDES
+	fsl_serdes_init();
+#endif
+	return 0;
+}
+
+int timer_init(void)
+{
+	u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+#ifdef COUNTER_FREQUENCY_REAL
+	unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
+
+	/* Update with accurate clock frequency */
+	asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
+#endif
+
+	/*  Enable clock for timer. This is a global setting. */
+	out_le32(cntcr, 0x1);
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
+	u32 val;
+
+	/* Raise RESET_REQ_B */
+	val = in_le32(rstcr);
+	val |= 0x02;
+	out_be32(rstcr, val);
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/fdt.c b/arch/arm/cpu/armv8/fsl-lsch2/fdt.c
new file mode 100644
index 0000000..015ad76
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch2/fdt.c
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+void ft_cpu_setup(void *blob, bd_t *bd)
+{
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-lsch2/fsl_lsch2_serdes.c
new file mode 100644
index 0000000..4832e92
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch2/fsl_lsch2_serdes.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch-fsl-lsch2/immap_lsch2.h>
+
+#ifdef CONFIG_SYS_FSL_SRDS_1
+static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
+#endif
+
+int is_serdes_configured(enum srds_prtcl device)
+{
+	int ret = 0;
+
+#ifdef CONFIG_SYS_FSL_SRDS_1
+	ret |= serdes1_prtcl_map[device];
+#endif
+
+	return !!ret;
+}
+
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 cfg = in_be32(&gur->rcwsr[4]);
+	int i;
+
+	switch (sd) {
+#ifdef CONFIG_SYS_FSL_SRDS_1
+	case FSL_SRDS_1:
+		cfg &= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+		cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+		break;
+#endif
+	default:
+		printf("invalid SerDes%d\n", sd);
+		break;
+	}
+
+	/* Is serdes enabled at all? */
+	if (unlikely(cfg == 0))
+		return -ENODEV;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (serdes_get_prtcl(sd, cfg, i) == device)
+			return i;
+	}
+
+	return -ENODEV;
+}
+
+int get_serdes_protocol(void)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 cfg = in_be32(&gur->rcwsr[4]) &
+			  FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+	cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	return cfg;
+}
+
+const char *serdes_clock_to_string(u32 clock)
+{
+	switch (clock) {
+	case SRDS_PLLCR0_RFCK_SEL_100:
+		return "100";
+	case SRDS_PLLCR0_RFCK_SEL_125:
+		return "125";
+	case SRDS_PLLCR0_RFCK_SEL_156_25:
+		return "156.25";
+	default:
+		return "100";
+	}
+}
+
+void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
+		u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 cfg;
+	int lane;
+
+	memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
+
+	cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
+	cfg >>= sd_prctl_shift;
+	printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
+
+	if (!is_serdes_prtcl_valid(sd, cfg))
+		printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
+
+	for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+		enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
+		if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
+			debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
+		else
+			serdes_prtcl_map[lane_prtcl] = 1;
+	}
+}
+
+void fsl_serdes_init(void)
+{
+#ifdef CONFIG_SYS_FSL_SRDS_1
+	serdes_init(FSL_SRDS_1,
+		    CONFIG_SYS_FSL_SERDES_ADDR,
+		    FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK,
+		    FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
+		    serdes1_prtcl_map);
+#endif
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch2/lowlevel.S
new file mode 100644
index 0000000..606388c
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch2/lowlevel.S
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Extracted from armv8/start.S
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/gic.h>
+#include <asm/macro.h>
+
+ENTRY(lowlevel_init)
+	mov	x29, lr			/* Save LR */
+
+	/* Set the SMMU page size in the sACR register */
+	ldr	x1, =SMMU_BASE
+	ldr	w0, [x1, #0x10]
+	orr	w0, w0, #1 << 16  /* set sACR.pagesize to indicate 64K page */
+	str	w0, [x1, #0x10]
+
+	/* Initialize GIC Secure Bank Status */
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+	branch_if_slave x0, 1f
+	ldr	x0, =GICD_BASE
+	bl	gic_init_secure
+1:
+#ifdef CONFIG_GICV3
+	ldr	x0, =GICR_BASE
+	bl	gic_init_secure_percpu
+#elif defined(CONFIG_GICV2)
+	ldr	x0, =GICD_BASE
+	ldr	x1, =GICC_BASE
+	bl	gic_init_secure_percpu
+#endif
+#endif
+
+	branch_if_master x0, x1, 1f
+
+	/*
+	 * Slave should wait for master clearing spin table.
+	 * This sync prevent salves observing incorrect
+	 * value of spin table and jumping to wrong place.
+	 */
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+#ifdef CONFIG_GICV2
+	ldr	x0, =GICC_BASE
+#endif
+	bl	gic_wait_for_interrupt
+#endif
+
+	/*
+	 * All processors will enter EL2 and optionally EL1.
+	 */
+	bl	armv8_switch_to_el2
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+	bl	armv8_switch_to_el1
+#endif
+	b	2f
+
+1:
+	/* Set Non Secure access for all devices protected via TZPC */
+	ldr	x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
+	mov	w0, #0xFF		/* Set decode region to NS, Bits[7:0] */
+	str	w0, [x1]
+
+	ldr	x1, =TZPCDECPROT_1_SET_BASE /* Decode Protection-1 Set Reg */
+	mov	w0, #0xFF		/* Set decode region to NS, Bits[7:0] */
+	str	w0, [x1]
+
+	ldr	x1, =TZPCDECPROT_2_SET_BASE /* Decode Protection-2 Set Reg */
+	mov	w0, #0xFF		/* Set decode region to NS, Bits[7:0] */
+	str	w0, [x1]
+
+	/* Entire SRAM as NS */
+	ldr	x1, =TZPCR0SIZE_BASE	/* Secure RAM region size Reg */
+	mov	w0, #0x00000000		/* 0x00000000 = no secure region */
+	str	w0, [x1]
+
+	/* Set TZASC so that:
+	 * a. We use only Region0 whose global secure write/read is EN
+	 * b. We use only Region0 whose NSAID write/read is EN
+	 *
+	 * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
+	 * 	 placeholders.
+	 */
+	ldr	x1, =TZASC_GATE_KEEPER(0)
+	ldr	x0, [x1]		/* Filter 0 Gate Keeper Register */
+	orr	x0, x0, #1 << 0		/* Set open_request for Filter 0 */
+	str	x0, [x1]
+
+	ldr	x1, =TZASC_GATE_KEEPER(1)
+	ldr	x0, [x1]		/* Filter 0 Gate Keeper Register */
+	orr	x0, x0, #1 << 0		/* Set open_request for Filter 0 */
+	str	x0, [x1]
+
+	ldr	x1, =TZASC_REGION_ATTRIBUTES_0(0)
+	ldr	x0, [x1]		/* Region-0 Attributes Register */
+	orr	x0, x0, #1 << 31	/* Set Sec global write en, Bit[31] */
+	orr	x0, x0, #1 << 30	/* Set Sec global read en, Bit[30] */
+	str	x0, [x1]
+
+	ldr	x1, =TZASC_REGION_ATTRIBUTES_0(1)
+	ldr	x0, [x1]		/* Region-1 Attributes Register */
+	orr	x0, x0, #1 << 31	/* Set Sec global write en, Bit[31] */
+	orr	x0, x0, #1 << 30	/* Set Sec global read en, Bit[30] */
+	str	x0, [x1]
+
+	ldr	x1, =TZASC_REGION_ID_ACCESS_0(0)
+	ldr	w0, [x1]		/* Region-0 Access Register */
+	mov	w0, #0xFFFFFFFF		/* Set nsaid_wr_en and nsaid_rd_en */
+	str	w0, [x1]
+
+	ldr	x1, =TZASC_REGION_ID_ACCESS_0(1)
+	ldr	w0, [x1]		/* Region-1 Attributes Register */
+	mov	w0, #0xFFFFFFFF		/* Set nsaid_wr_en and nsaid_rd_en */
+	str	w0, [x1]
+2:
+	mov	lr, x29			/* Restore LR */
+	ret
+ENDPROC(lowlevel_init)
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/ls1043a_serdes.c b/arch/arm/cpu/armv8/fsl-lsch2/ls1043a_serdes.c
new file mode 100644
index 0000000..818285f
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch2/ls1043a_serdes.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch-fsl-lsch2/immap_lsch2.h>
+
+struct serdes_config {
+	u32 protocol;
+	u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+	/* SerDes 1 */
+	{0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3} },
+	{0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} },
+	{0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3} },
+	{0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA1} },
+	{0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
+	{0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
+	{0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5,
+		  PCIE3} },
+	{0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
+	{0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA1} },
+	{0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} },
+	{0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA1} },
+	{0x7000, {PCIE1, PCIE1, PCIE1, PCIE1} },
+	{0x9998, {PCIE1, PCIE2, PCIE3, SATA1} },
+	{0x6058, {PCIE1, PCIE1, PCIE2, SATA1} },
+	{0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3} },
+	{0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3} },
+	{0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3} },
+	{0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5,
+		  SGMII_FM1_DTSEC6} },
+	{}
+};
+
+static struct serdes_config *serdes_cfg_tbl[] = {
+	serdes1_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == cfg)
+			return ptr->lanes[lane];
+		ptr++;
+	}
+
+	return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+	int i;
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == prtcl)
+			break;
+		ptr++;
+	}
+
+	if (!ptr->protocol)
+		return 0;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (ptr->lanes[i] != NONE)
+			return 1;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/soc.c b/arch/arm/cpu/armv8/fsl-lsch2/soc.c
new file mode 100644
index 0000000..8f010ae
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch2/soc.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_ifc.h>
+#include <asm/arch-fsl-lsch2/soc.h>
+#include <asm/io.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_lsch2_early_init_f(void)
+{
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+
+#ifdef CONFIG_FSL_IFC
+	init_early_memctl_regs();	/* tighten IFC timing */
+#endif
+
+	/*
+	 * Enable snoop requests and DVM message requests for
+	 * Slave insterface S4 (A53 core cluster)
+	 */
+	out_le32(&cci->slave[4].snoop_ctrl,
+		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	return 0;
+}
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/speed.c b/arch/arm/cpu/armv8/fsl-lsch2/speed.c
new file mode 100644
index 0000000..197cc0e
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch2/speed.c
@@ -0,0 +1,137 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/compiler.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/arch-fsl-lsch2/immap_lsch2.h>
+#include <asm/arch/clock.h>
+#include <fsl_ifc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
+#define CONFIG_SYS_FSL_NUM_CC_PLLS      2
+#endif
+
+void get_sys_info(struct sys_info *sys_info)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#ifdef CONFIG_FSL_IFC
+	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+	u32 ccr;
+#endif
+	struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
+	unsigned int cpu;
+	const u8 core_cplx_pll[8] = {
+		[0] = 0,	/* CC1 PPL / 1 */
+		[1] = 0,	/* CC1 PPL / 2 */
+		[4] = 1,	/* CC2 PPL / 1 */
+		[5] = 1,	/* CC2 PPL / 2 */
+	};
+
+	const u8 core_cplx_pll_div[8] = {
+		[0] = 1,	/* CC1 PPL / 1 */
+		[1] = 2,	/* CC1 PPL / 2 */
+		[4] = 1,	/* CC2 PPL / 1 */
+		[5] = 2,	/* CC2 PPL / 2 */
+	};
+
+	uint i;
+	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
+	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
+	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+
+	sys_info->freq_systembus = sysclk;
+#ifdef CONFIG_DDR_CLK_FREQ
+	sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#else
+	sys_info->freq_ddrbus = sysclk;
+#endif
+
+	sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >>
+			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
+			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
+	sys_info->freq_ddrbus *= (in_be32(&gur->rcwsr[0]) >>
+			FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
+			FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
+
+	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
+		ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
+		if (ratio[i] > 4)
+			freq_c_pll[i] = sysclk * ratio[i];
+		else
+			freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
+	}
+
+	for (cpu = 0; cpu < CONFIG_MAX_CPUS; cpu++) {
+		u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
+				& 0xf;
+		u32 cplx_pll = core_cplx_pll[c_pll_sel];
+
+		sys_info->freq_processor[cpu] =
+			freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
+	}
+
+#define HWA_CGA_M1_CLK_SEL	0xe0000000
+#define HWA_CGA_M1_CLK_SHIFT	29
+
+#define HWA_CGA_M2_CLK_SEL	0x00000007
+#define HWA_CGA_M2_CLK_SHIFT	0
+
+#if defined(CONFIG_FSL_IFC)
+	ccr = in_le32(&ifc_regs.gregs->ifc_ccr);
+	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
+
+	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+#endif
+}
+
+int get_clocks(void)
+{
+	struct sys_info sys_info;
+
+	get_sys_info(&sys_info);
+	gd->cpu_clk = sys_info.freq_processor[0];
+	gd->bus_clk = sys_info.freq_systembus;
+	gd->mem_clk = sys_info.freq_ddrbus;
+
+	if (gd->cpu_clk != 0)
+		return 0;
+	else
+		return 1;
+}
+
+ulong get_bus_freq(ulong dummy)
+{
+	return gd->bus_clk;
+}
+
+ulong get_ddr_freq(ulong dummy)
+{
+	return gd->mem_clk;
+}
+
+int get_serial_clock(void)
+{
+	return gd->bus_clk;
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+	switch (clk) {
+	case MXC_I2C_CLK:
+		return get_bus_freq(0);
+	case MXC_DSPI_CLK:
+		return get_bus_freq(0);
+	case MXC_UART_CLK:
+		return get_bus_freq(0);
+	default:
+		printf("Unsupported clock\n");
+	}
+	return 0;
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/speed.h b/arch/arm/cpu/armv8/fsl-lsch2/speed.h
new file mode 100644
index 0000000..15af5b9
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch2/speed.h
@@ -0,0 +1,7 @@
+/*
+ * Copyright 2014, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+void get_sys_info(struct sys_info *sys_info);
diff --git a/arch/arm/include/asm/arch-fsl-lsch2/clock.h b/arch/arm/include/asm/arch-fsl-lsch2/clock.h
new file mode 100644
index 0000000..705c9bf
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-lsch2/clock.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#ifndef __ASM_ARCH_FSL_LSCH2_CLOCK_H_
+#define __ASM_ARCH_FSL_LSCH2_CLOCK_H_
+
+#include <common.h>
+
+enum mxc_clock {
+	MXC_ARM_CLK = 0,
+	MXC_BUS_CLK,
+	MXC_UART_CLK,
+	MXC_ESDHC_CLK,
+	MXC_I2C_CLK,
+	MXC_DSPI_CLK,
+};
+
+unsigned int mxc_get_clock(enum mxc_clock clk);
+
+#endif /* __ASM_ARCH_FSL_LSCH2_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-lsch2/config.h b/arch/arm/include/asm/arch-fsl-lsch2/config.h
new file mode 100644
index 0000000..2270ee1
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-lsch2/config.h
@@ -0,0 +1,150 @@
+/*
+ * Copyright 2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_FSL_LSCH2_CONFIG_
+#define _ASM_ARMV8_FSL_LSCH2_CONFIG_
+
+#define CONFIG_SYS_FSL_OCRAM_BASE	0x10000000	/* initial RAM */
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+/* Link Definitions */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+
+#define CONFIG_SYS_IMMR				0x01000000
+#define CONFIG_SYS_DCSRBAR			0x20000000
+#define CONFIG_SYS_DCSR_DCFG_ADDR	(CONFIG_SYS_DCSRBAR + 0x00220000)
+
+#define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
+#define CONFIG_SYS_CCI400_ADDR			(CONFIG_SYS_IMMR + 0x00180000)
+#define CONFIG_SYS_GIC400_ADDR			(CONFIG_SYS_IMMR + 0x00400000)
+#define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
+#define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x00560000)
+#define CONFIG_SYS_FSL_CSU_ADDR			(CONFIG_SYS_IMMR + 0x00510000)
+#define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
+#define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00ee00b0)
+#define CONFIG_SYS_FSL_SCFG_ADDR		(CONFIG_SYS_IMMR + 0x00570000)
+#define CONFIG_SYS_FSL_FMAN_ADDR		(CONFIG_SYS_IMMR + 0x00a00000)
+#define CONFIG_SYS_FSL_SERDES_ADDR		(CONFIG_SYS_IMMR + 0x00ea0000)
+#define CONFIG_SYS_FSL_DCFG_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
+#define CONFIG_SYS_FSL_CLK_ADDR			(CONFIG_SYS_IMMR + 0x00ee1000)
+#define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
+#define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011c0600)
+#define CONFIG_SYS_NS16550_COM3			(CONFIG_SYS_IMMR + 0x011d0500)
+#define CONFIG_SYS_NS16550_COM4			(CONFIG_SYS_IMMR + 0x011d0600)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x01f00000)
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR		(CONFIG_SYS_IMMR + 0x02000000)
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
+#define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
+#define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)
+#define CONFIG_SYS_FSL_SEC_ADDR			(CONFIG_SYS_IMMR + 0x700000)
+#define CONFIG_SYS_FSL_JR0_ADDR			(CONFIG_SYS_IMMR + 0x710000)
+#define CONFIG_SYS_SNVS_ADDR			(CONFIG_SYS_IMMR + 0xe90000)
+#define CONFIG_SYS_SFP_ADDR			(CONFIG_SYS_IMMR + 0xe80200)
+
+#define CONFIG_SYS_FSL_TIMER_ADDR		0x02b00000
+
+#define I2C1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01180000)
+#define I2C2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01190000)
+#define I2C3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x011a0000)
+#define I2C4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x011b0000)
+
+#define WDOG1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01ad0000)
+
+#define QSPI0_BASE_ADDR				(CONFIG_SYS_IMMR + 0x00550000)
+#define DSPI1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01100000)
+
+#define LPUART_BASE				(CONFIG_SYS_IMMR + 0x01950000)
+
+#define AHCI_BASE_ADDR				(CONFIG_SYS_IMMR + 0x02200000)
+
+#define CONFIG_SYS_PCIE1_PHYS_ADDR		0x4000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR		0x4800000000ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR		0x5000000000ULL
+
+/* SMMU Defintions */
+#define SMMU_BASE				0x09000000
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE              0x01401000
+#define GICC_BASE              0x01402000
+
+/* TZ Protection Controller Definitions */
+#define TZPC_BASE				0x02200000
+#define TZPCR0SIZE_BASE				(TZPC_BASE)
+#define TZPCDECPROT_0_STAT_BASE			(TZPC_BASE + 0x800)
+#define TZPCDECPROT_0_SET_BASE			(TZPC_BASE + 0x804)
+#define TZPCDECPROT_0_CLR_BASE			(TZPC_BASE + 0x808)
+#define TZPCDECPROT_1_STAT_BASE			(TZPC_BASE + 0x80C)
+#define TZPCDECPROT_1_SET_BASE			(TZPC_BASE + 0x810)
+#define TZPCDECPROT_1_CLR_BASE			(TZPC_BASE + 0x814)
+#define TZPCDECPROT_2_STAT_BASE			(TZPC_BASE + 0x818)
+#define TZPCDECPROT_2_SET_BASE			(TZPC_BASE + 0x81C)
+#define TZPCDECPROT_2_CLR_BASE			(TZPC_BASE + 0x820)
+
+/* TZ Address Space Controller Definitions */
+#define TZASC1_BASE			0x01100000	/* as per CCSR map. */
+#define TZASC2_BASE			0x01110000	/* as per CCSR map. */
+#define TZASC3_BASE			0x01120000	/* as per CCSR map. */
+#define TZASC4_BASE			0x01130000	/* as per CCSR map. */
+#define TZASC_BUILD_CONFIG_REG(x)	((TZASC1_BASE + (x * 0x10000)))
+#define TZASC_ACTION_REG(x)		((TZASC1_BASE + (x * 0x10000)) + 0x004)
+#define TZASC_GATE_KEEPER(x)		((TZASC1_BASE + (x * 0x10000)) + 0x008)
+#define TZASC_REGION_BASE_LOW_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x100)
+#define TZASC_REGION_BASE_HIGH_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x104)
+#define TZASC_REGION_TOP_LOW_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x108)
+#define TZASC_REGION_TOP_HIGH_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x10C)
+#define TZASC_REGION_ATTRIBUTES_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x110)
+#define TZASC_REGION_ID_ACCESS_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x114)
+
+#define CONFIG_SYS_FSL_DDR_BE
+#define CONFIG_VERY_BIG_RAM
+#ifdef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_FSL_DDRC_GEN4
+#else
+#define CONFIG_SYS_FSL_DDRC_ARM_GEN3    /* Enable Freescale ARM DDR3 driver */
+#endif
+#define CONFIG_SYS_FSL_DDR              /* Freescale DDR driver */
+#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_IFC_BE
+#define CONFIG_SYS_FSL_ESDHC_BE
+#define CONFIG_SYS_FSL_WDOG_BE
+#define CONFIG_SYS_FSL_DSPI_BE
+#define CONFIG_SYS_FSL_QSPI_BE
+
+#define QE_MURAM_SIZE          0x6000UL
+#define MAX_QE_RISC            1
+#define QE_NUM_OF_SNUM         28
+
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_PCIE_COMPAT		"fsl,qoriq-pcie-v2.4"
+
+#ifdef CONFIG_LS1043A
+#define CONFIG_MAX_CPUS				4
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_NUM_FMAN			1
+#define CONFIG_SYS_NUM_FM1_DTSEC		7
+#define CONFIG_SYS_NUM_FM1_10GEC		1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT		4
+#define CONFIG_NUM_DDR_CONTROLLERS		1
+#define CONFIG_SYS_FSL_DDR_VER			FSL_DDR_VER_5_0
+#define CONFIG_SYS_CCSRBAR_DEFAULT		0x01000000
+#define CONFIG_SYS_FSL_SEC_COMPAT		5
+#else
+#error SoC not defined
+#endif
+
+#define CONFIG_SYS_FSL_SFP_VER_3_2
+#define CONFIG_SYS_FSL_SNVS_LE
+#define CONFIG_SYS_FSL_SEC_LE
+#define CONFIG_SYS_FSL_SFP_BE
+#define CONFIG_SYS_FSL_SRK_LE
+#define CONFIG_KEY_REVOCATION
+
+#endif /* _ASM_ARMV8_FSL_LSCH2_CONFIG_ */
diff --git a/arch/arm/include/asm/arch-fsl-lsch2/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-lsch2/fsl_serdes.h
new file mode 100644
index 0000000..6d348e6
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-lsch2/fsl_serdes.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_SERDES_H__
+#define __FSL_SERDES_H__
+
+#include <config.h>
+
+enum srds_prtcl {
+	NONE = 0,
+	PCIE1,
+	PCIE2,
+	PCIE3,
+	PCIE4,
+	SATA1,
+	SATA2,
+	SRIO1,
+	SRIO2,
+	SGMII_FM1_DTSEC1,
+	SGMII_FM1_DTSEC2,
+	SGMII_FM1_DTSEC3,
+	SGMII_FM1_DTSEC4,
+	SGMII_FM1_DTSEC5,
+	SGMII_FM1_DTSEC6,
+	SGMII_FM1_DTSEC9,
+	SGMII_FM1_DTSEC10,
+	SGMII_FM2_DTSEC1,
+	SGMII_FM2_DTSEC2,
+	SGMII_FM2_DTSEC3,
+	SGMII_FM2_DTSEC4,
+	SGMII_FM2_DTSEC5,
+	SGMII_FM2_DTSEC6,
+	SGMII_FM2_DTSEC9,
+	SGMII_FM2_DTSEC10,
+	SGMII_TSEC1,
+	SGMII_TSEC2,
+	SGMII_TSEC3,
+	SGMII_TSEC4,
+	XAUI_FM1,
+	XAUI_FM2,
+	AURORA,
+	CPRI1,
+	CPRI2,
+	CPRI3,
+	CPRI4,
+	CPRI5,
+	CPRI6,
+	CPRI7,
+	CPRI8,
+	XAUI_FM1_MAC9,
+	XAUI_FM1_MAC10,
+	XAUI_FM2_MAC9,
+	XAUI_FM2_MAC10,
+	HIGIG_FM1_MAC9,
+	HIGIG_FM1_MAC10,
+	HIGIG_FM2_MAC9,
+	HIGIG_FM2_MAC10,
+	QSGMII_FM1_A,		/* A indicates MACs 1,2,5,6 */
+	QSGMII_FM1_B,		/* B indicates MACs 5,6,9,10 */
+	QSGMII_FM2_A,
+	QSGMII_FM2_B,
+	XFI_FM1_MAC1,
+	XFI_FM1_MAC2,
+	XFI_FM1_MAC9,
+	XFI_FM1_MAC10,
+	XFI_FM2_MAC9,
+	XFI_FM2_MAC10,
+	INTERLAKEN,
+	QSGMII_SW1_A,		/* Indicates ports on L2 Switch */
+	QSGMII_SW1_B,
+	SGMII_2500_FM1_DTSEC1,
+	SGMII_2500_FM1_DTSEC2,
+	SGMII_2500_FM1_DTSEC3,
+	SGMII_2500_FM1_DTSEC4,
+	SGMII_2500_FM1_DTSEC5,
+	SGMII_2500_FM1_DTSEC6,
+	SGMII_2500_FM1_DTSEC9,
+	SGMII_2500_FM1_DTSEC10,
+	SGMII_2500_FM2_DTSEC1,
+	SGMII_2500_FM2_DTSEC2,
+	SGMII_2500_FM2_DTSEC3,
+	SGMII_2500_FM2_DTSEC4,
+	SGMII_2500_FM2_DTSEC5,
+	SGMII_2500_FM2_DTSEC6,
+	SGMII_2500_FM2_DTSEC9,
+	SGMII_2500_FM2_DTSEC10,
+	SERDES_PRCTL_COUNT
+};
+
+enum srds {
+	FSL_SRDS_1  = 0,
+};
+
+int is_serdes_configured(enum srds_prtcl device);
+void fsl_serdes_init(void);
+const char *serdes_clock_to_string(u32 clock);
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
+int is_serdes_prtcl_valid(int serdes, u32 prtcl);
+int get_serdes_protocol(void);
+
+#endif /* __FSL_SERDES_H__ */
diff --git a/arch/arm/include/asm/arch-fsl-lsch2/gpio.h b/arch/arm/include/asm/arch-fsl-lsch2/gpio.h
new file mode 100644
index 0000000..7d0f057
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-lsch2/gpio.h
@@ -0,0 +1,9 @@
+/*
+ * (C) Copyright 2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_FSL_LSCH2_GPIO_H_
+#define _ASM_ARMV8_FSL_LSCH2_GPIO_H_
+#endif	/* _ASM_ARMV8_FSL_LSCH2_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-lsch2/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-lsch2/immap_lsch2.h
new file mode 100644
index 0000000..2e692b9
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-lsch2/immap_lsch2.h
@@ -0,0 +1,496 @@
+/*
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARCH_FSL_LSCH2_IMMAP_H__
+#define __ARCH_FSL_LSCH2_IMMAP_H__
+
+#include <fsl_immap.h>
+
+#define IS_E_PROCESSOR(svr)	(!(svr & 0x100))
+
+#define TP_ITYP_AV              0x00000001      /* Initiator available */
+#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1)      /* Initiator Type */
+#define TP_ITYP_TYPE_ARM        0x0
+#define TP_ITYP_TYPE_PPC        0x1             /* PowerPC */
+#define TP_ITYP_TYPE_OTHER      0x2             /* StarCore DSP */
+#define TP_ITYP_TYPE_HA         0x3             /* HW Accelerator */
+#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3)     /* # threads */
+#define TP_ITYP_VER(x)  (((x) & 0xe0) >> 5)     /* Initiator Version */
+#define TY_ITYP_VER_A7          0x1
+#define TY_ITYP_VER_A53         0x2
+#define TY_ITYP_VER_A57         0x3
+
+#define TP_CLUSTER_EOC_MASK	0xc0000000      /* end of clusters mask */
+#define TP_CLUSTER_INIT_MASK    0x0000003f      /* initiator mask */
+#define TP_INIT_PER_CLUSTER     4
+
+/*
+ * Define default values for some CCSR macros to make header files cleaner*
+ *
+ * To completely disable CCSR relocation in a board header file, define
+ * CONFIG_SYS_CCSR_DO_NOT_RELOCATE.  This will force CONFIG_SYS_CCSRBAR_PHYS
+ * to a value that is the same as CONFIG_SYS_CCSRBAR.
+ */
+
+#ifdef CONFIG_SYS_CCSRBAR_PHYS
+#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly.  Use \
+CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
+#endif
+
+#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR		CONFIG_SYS_CCSRBAR_DEFAULT
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0xf
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
+#endif
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR_DEFAULT
+#endif
+
+#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
+				 CONFIG_SYS_CCSRBAR_PHYS_LOW)
+
+struct sys_info {
+	unsigned long freq_processor[CONFIG_MAX_CPUS];
+	unsigned long freq_systembus;
+	unsigned long freq_ddrbus;
+	unsigned long freq_localbus;
+	unsigned long freq_sdhc;
+#ifdef CONFIG_SYS_DPAA_FMAN
+	unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
+#endif
+	unsigned long freq_qman;
+};
+
+#define CONFIG_SYS_FSL_FM1_OFFSET		0xa00000
+#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET	0xa88000
+#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET	0xa89000
+#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET	0xa8a000
+#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET	0xa8b000
+#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET	0xa8c000
+#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET	0xa8d000
+
+#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET	0xae0000
+#define CONFIG_SYS_FSL_FM1_ADDR			\
+		(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
+#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR		\
+		(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
+
+/* Device Configuration and Pin Control */
+struct ccsr_gur {
+	u32     porsr1;         /* POR status 1 */
+#define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK	0xFF800000
+	u32     porsr2;         /* POR status 2 */
+	u8      res_008[0x20-0x8];
+	u32     gpporcr1;       /* General-purpose POR configuration */
+	u32	gpporcr2;
+#define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT	25
+#define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK	0x1F
+#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT	20
+#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK	0x1F
+	u32     dcfg_fusesr;    /* Fuse status register */
+	u8      res_02c[0x70-0x2c];
+	u32     devdisr;        /* Device disable control */
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_1	0x80000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_2	0x40000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_3	0x20000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_4	0x10000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_5	0x08000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_6	0x04000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_9	0x00800000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_10	0x00400000
+#define FSL_CHASSIS2_DEVDISR2_10GEC1_1	0x00800000
+#define FSL_CHASSIS2_DEVDISR2_10GEC1_2	0x00400000
+#define FSL_CHASSIS2_DEVDISR2_10GEC1_3	0x80000000
+#define FSL_CHASSIS2_DEVDISR2_10GEC1_4	0x40000000
+	u32     devdisr2;       /* Device disable control 2 */
+	u32     devdisr3;       /* Device disable control 3 */
+	u32     devdisr4;       /* Device disable control 4 */
+	u32     devdisr5;       /* Device disable control 5 */
+	u32     devdisr6;       /* Device disable control 6 */
+	u32     devdisr7;       /* Device disable control 7 */
+	u8      res_08c[0x94-0x8c];
+	u32     coredisru;      /* uppper portion for support of 64 cores */
+	u32     coredisrl;      /* lower portion for support of 64 cores */
+	u8      res_09c[0xa0-0x9c];
+	u32     pvr;            /* Processor version */
+	u32     svr;            /* System version */
+	u32     mvr;            /* Manufacturing version */
+	u8	res_0ac[0xb0-0xac];
+	u32	rstcr;		/* Reset control */
+	u32	rstrqpblsr;	/* Reset request preboot loader status */
+	u8	res_0b8[0xc0-0xb8];
+	u32	rstrqmr1;	/* Reset request mask */
+	u8	res_0c4[0xc8-0xc4];
+	u32	rstrqsr1;	/* Reset request status */
+	u8	res_0cc[0xd4-0xcc];
+	u32	rstrqwdtmrl;	/* Reset request WDT mask */
+	u8	res_0d8[0xdc-0xd8];
+	u32	rstrqwdtsrl;	/* Reset request WDT status */
+	u8	res_0e0[0xe4-0xe0];
+	u32	brrl;		/* Boot release */
+	u8      res_0e8[0x100-0xe8];
+	u32     rcwsr[16];      /* Reset control word status */
+#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT	25
+#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK	0x1f
+#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT	16
+#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK	0x3f
+#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK	0xffff0000
+#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT	16
+	u8      res_140[0x200-0x140];
+	u32     scratchrw[4];  /* Scratch Read/Write */
+	u8      res_210[0x300-0x210];
+	u32     scratchw1r[4];  /* Scratch Read (Write once) */
+	u8      res_310[0x400-0x310];
+	u32	crstsr[12];
+	u8	res_430[0x500-0x430];
+
+	/* PCI Express n Logical I/O Device Number register */
+	u32 dcfg_ccsr_pex1liodnr;
+	u32 dcfg_ccsr_pex2liodnr;
+	u32 dcfg_ccsr_pex3liodnr;
+	u32 dcfg_ccsr_pex4liodnr;
+	/* RIO n Logical I/O Device Number register */
+	u32 dcfg_ccsr_rio1liodnr;
+	u32 dcfg_ccsr_rio2liodnr;
+	u32 dcfg_ccsr_rio3liodnr;
+	u32 dcfg_ccsr_rio4liodnr;
+	/* USB Logical I/O Device Number register */
+	u32 dcfg_ccsr_usb1liodnr;
+	u32 dcfg_ccsr_usb2liodnr;
+	u32 dcfg_ccsr_usb3liodnr;
+	u32 dcfg_ccsr_usb4liodnr;
+	/* SD/MMC Logical I/O Device Number register */
+	u32 dcfg_ccsr_sdmmc1liodnr;
+	u32 dcfg_ccsr_sdmmc2liodnr;
+	u32 dcfg_ccsr_sdmmc3liodnr;
+	u32 dcfg_ccsr_sdmmc4liodnr;
+	/* RIO Message Unit Logical I/O Device Number register */
+	u32 dcfg_ccsr_riomaintliodnr;
+
+	u8      res_544[0x550-0x544];
+	u32	sataliodnr[4];
+	u8	res_560[0x570-0x560];
+
+	u32 dcfg_ccsr_misc1liodnr;
+	u32 dcfg_ccsr_misc2liodnr;
+	u32 dcfg_ccsr_misc3liodnr;
+	u32 dcfg_ccsr_misc4liodnr;
+	u32 dcfg_ccsr_dma1liodnr;
+	u32 dcfg_ccsr_dma2liodnr;
+	u32 dcfg_ccsr_dma3liodnr;
+	u32 dcfg_ccsr_dma4liodnr;
+	u32 dcfg_ccsr_spare1liodnr;
+	u32 dcfg_ccsr_spare2liodnr;
+	u32 dcfg_ccsr_spare3liodnr;
+	u32 dcfg_ccsr_spare4liodnr;
+	u8	res_5a0[0x600-0x5a0];
+	u32 dcfg_ccsr_pblsr;
+
+	u32	pamubypenr;
+	u32	dmacr1;
+
+	u8	res_60c[0x610-0x60c];
+	u32 dcfg_ccsr_gensr1;
+	u32 dcfg_ccsr_gensr2;
+	u32 dcfg_ccsr_gensr3;
+	u32 dcfg_ccsr_gensr4;
+	u32 dcfg_ccsr_gencr1;
+	u32 dcfg_ccsr_gencr2;
+	u32 dcfg_ccsr_gencr3;
+	u32 dcfg_ccsr_gencr4;
+	u32 dcfg_ccsr_gencr5;
+	u32 dcfg_ccsr_gencr6;
+	u32 dcfg_ccsr_gencr7;
+	u8	res_63c[0x658-0x63c];
+	u32 dcfg_ccsr_cgensr1;
+	u32 dcfg_ccsr_cgensr0;
+	u8	res_660[0x678-0x660];
+	u32 dcfg_ccsr_cgencr1;
+
+	u32 dcfg_ccsr_cgencr0;
+	u8	res_680[0x700-0x680];
+	u32 dcfg_ccsr_sriopstecr;
+	u32 dcfg_ccsr_dcsrcr;
+
+	u8      res_708[0x740-0x708];   /* add more registers when needed */
+	u32     tp_ityp[64];    /* Topology Initiator Type Register */
+	struct {
+		u32     upper;
+		u32     lower;
+	} tp_cluster[16];
+	u8      res_8c0[0xa00-0x8c0];   /* add more registers when needed */
+	u32 dcfg_ccsr_qmbm_warmrst;
+	u8      res_a04[0xa20-0xa04];   /* add more registers when needed */
+	u32 dcfg_ccsr_reserved0;
+	u32 dcfg_ccsr_reserved1;
+};
+
+#define SCFG_QSPI_CLKSEL		0x40100000
+#define SCFG_USBDRVVBUS_SELCR_USB1	0x00000000
+#define SCFG_USBDRVVBUS_SELCR_USB2	0x00000001
+#define SCFG_USBDRVVBUS_SELCR_USB3	0x00000002
+#define SCFG_USBPWRFAULT_INACTIVE	0x00000000
+#define SCFG_USBPWRFAULT_SHARED		0x00000001
+#define SCFG_USBPWRFAULT_DEDICATED	0x00000002
+#define SCFG_USBPWRFAULT_USB3_SHIFT	4
+#define SCFG_USBPWRFAULT_USB2_SHIFT	2
+#define SCFG_USBPWRFAULT_USB1_SHIFT	0
+
+#define SCFG_SNPCNFGCR_SECRDSNP		0x80000000
+#define SCFG_SNPCNFGCR_SECWRSNP		0x40000000
+
+/* Supplemental Configuration Unit */
+struct ccsr_scfg {
+	u8 res_000[0x100-0x000];
+	u32 usb2_icid;
+	u32 usb3_icid;
+	u8 res_108[0x114-0x108];
+	u32 dma_icid;
+	u32 sata_icid;
+	u32 usb1_icid;
+	u32 qe_icid;
+	u32 sdhc_icid;
+	u32 edma_icid;
+	u32 etr_icid;
+	u32 core_sft_rst[4];
+	u8 res_140[0x158-0x140];
+	u32 altcbar;
+	u32 qspi_cfg;
+	u8 res_160[0x180-0x160];
+	u32 dmamcr;
+	u8 res_184[0x18c-0x184];
+	u32 debug_icid;
+	u8 res_190[0x1a4-0x190];
+	u32 snpcnfgcr;
+	u8 res_1a8[0x1ac-0x1a8];
+	u32 intpcr;
+	u8 res_1b0[0x204-0x1b0];
+	u32 coresrencr;
+	u8 res_208[0x220-0x208];
+	u32 rvbar0_0;
+	u32 rvbar0_1;
+	u32 rvbar1_0;
+	u32 rvbar1_1;
+	u32 rvbar2_0;
+	u32 rvbar2_1;
+	u32 rvbar3_0;
+	u32 rvbar3_1;
+	u32 lpmcsr;
+	u8 res_244[0x400-0x244];
+	u32 qspidqscr;
+	u32 ecgtxcmcr;
+	u32 sdhciovselcr;
+	u32 rcwpmuxcr0;
+	u32 usbdrvvbus_selcr;
+	u32 usbpwrfault_selcr;
+	u32 usb_refclk_selcr1;
+	u32 usb_refclk_selcr2;
+	u32 usb_refclk_selcr3;
+	u8 res_424[0x600-0x424];
+	u32 scratchrw[4];
+	u8 res_610[0x680-0x610];
+	u32 corebcr;
+	u8 res_684[0x1000-0x684];
+	u32 pex1msiir;
+	u32 pex1msir;
+	u8 res_1008[0x2000-0x1008];
+	u32 pex2;
+	u32 pex2msir;
+	u8 res_2008[0x3000-0x2008];
+	u32 pex3msiir;
+	u32 pex3msir;
+};
+
+/* Clocking */
+struct ccsr_clk {
+	struct {
+		u32 clkcncsr;	/* core cluster n clock control status */
+		u8  res_004[0x0c];
+		u32 clkcghwacsr; /* Clock generator n hardware accelerator */
+		u8  res_014[0x0c];
+	} clkcsr[4];
+	u8	res_040[0x780]; /* 0x100 */
+	struct {
+		u32 pllcngsr;
+		u8 res_804[0x1c];
+	} pllcgsr[2];
+	u8	res_840[0x1c0];
+	u32	clkpcsr;	/* 0xa00 Platform clock domain control/status */
+	u8	res_a04[0x1fc];
+	u32	pllpgsr;	/* 0xc00 Platform PLL General Status */
+	u8	res_c04[0x1c];
+	u32	plldgsr;	/* 0xc20 DDR PLL General Status */
+	u8	res_c24[0x3dc];
+};
+
+/* System Counter */
+struct sctr_regs {
+	u32 cntcr;
+	u32 cntsr;
+	u32 cntcv1;
+	u32 cntcv2;
+	u32 resv1[4];
+	u32 cntfid0;
+	u32 cntfid1;
+	u32 resv2[1002];
+	u32 counterid[12];
+};
+
+#define MAX_SERDES		1
+#define SRDS_MAX_LANES		4
+#define SRDS_MAX_BANK		2
+struct ccsr_serdes {
+	struct {
+		u32	rstctl;	/* Reset Control Register */
+#define SRDS_RSTCTL_RST		0x80000000
+#define SRDS_RSTCTL_RSTDONE	0x40000000
+#define SRDS_RSTCTL_RSTERR	0x20000000
+#define SRDS_RSTCTL_SWRST	0x10000000
+#define SRDS_RSTCTL_SDEN	0x00000020
+#define SRDS_RSTCTL_SDRST_B	0x00000040
+#define SRDS_RSTCTL_PLLRST_B	0x00000080
+		u32	pllcr0; /* PLL Control Register 0 */
+#define SRDS_PLLCR0_POFF		0x80000000
+#define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
+#define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
+#define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
+#define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
+#define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
+#define SRDS_PLLCR0_RFCK_SEL_122_88	0x50000000
+#define SRDS_PLLCR0_PLL_LCK		0x00800000
+#define SRDS_PLLCR0_FRATE_SEL_MASK	0x000f0000
+#define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_3_75	0x00050000
+#define SRDS_PLLCR0_FRATE_SEL_5_15	0x00060000
+#define SRDS_PLLCR0_FRATE_SEL_4		0x00070000
+#define SRDS_PLLCR0_FRATE_SEL_3_12	0x00090000
+#define SRDS_PLLCR0_FRATE_SEL_3		0x000a0000
+		u32	pllcr1; /* PLL Control Register 1 */
+#define SRDS_PLLCR1_PLL_BWSEL	0x08000000
+		u32	res_0c;	/* 0x00c */
+		u32	pllcr3;
+		u32	pllcr4;
+		u8	res_18[0x20-0x18];
+	} bank[2];
+	u8	res_40[0x90-0x40];
+	u32	srdstcalcr;	/* 0x90 TX Calibration Control */
+	u8	res_94[0xa0-0x94];
+	u32	srdsrcalcr;	/* 0xa0 RX Calibration Control */
+	u8	res_a4[0xb0-0xa4];
+	u32	srdsgr0;	/* 0xb0 General Register 0 */
+	u8	res_b4[0xe0-0xb4];
+	u32	srdspccr0;	/* 0xe0 Protocol Converter Config 0 */
+	u32	srdspccr1;	/* 0xe4 Protocol Converter Config 1 */
+	u32	srdspccr2;	/* 0xe8 Protocol Converter Config 2 */
+	u32	srdspccr3;	/* 0xec Protocol Converter Config 3 */
+	u32	srdspccr4;	/* 0xf0 Protocol Converter Config 4 */
+	u8	res_f4[0x100-0xf4];
+	struct {
+		u32	lnpssr;	/* 0x100, 0x120, ..., 0x1e0 */
+		u8	res_104[0x120-0x104];
+	} srdslnpssr[4];
+	u8	res_180[0x300-0x180];
+	u32	srdspexeqcr;
+	u32	srdspexeqpcr[11];
+	u8	res_330[0x400-0x330];
+	u32	srdspexapcr;
+	u8	res_404[0x440-0x404];
+	u32	srdspexbpcr;
+	u8	res_444[0x800-0x444];
+	struct {
+		u32	gcr0;	/* 0x800 General Control Register 0 */
+		u32	gcr1;	/* 0x804 General Control Register 1 */
+		u32	gcr2;	/* 0x808 General Control Register 2 */
+		u32	sscr0;
+		u32	recr0;	/* 0x810 Receive Equalization Control */
+		u32	recr1;
+		u32	tecr0;	/* 0x818 Transmit Equalization Control */
+		u32	sscr1;
+		u32	ttlcr0;	/* 0x820 Transition Tracking Loop Ctrl 0 */
+		u8	res_824[0x83c-0x824];
+		u32	tcsr3;
+	} lane[4];	/* Lane A, B, C, D, E, F, G, H */
+	u8	res_a00[0x1000-0xa00];	/* from 0xa00 to 0xfff */
+};
+
+#define CCI400_CTRLORD_TERM_BARRIER	0x00000008
+#define CCI400_CTRLORD_EN_BARRIER	0
+#define CCI400_SHAORD_NON_SHAREABLE	0x00000002
+#define CCI400_DVM_MESSAGE_REQ_EN	0x00000002
+#define CCI400_SNOOP_REQ_EN		0x00000001
+
+/* CCI-400 registers */
+struct ccsr_cci400 {
+	u32 ctrl_ord;			/* Control Override */
+	u32 spec_ctrl;			/* Speculation Control */
+	u32 secure_access;		/* Secure Access */
+	u32 status;			/* Status */
+	u32 impr_err;			/* Imprecise Error */
+	u8 res_14[0x100 - 0x14];
+	u32 pmcr;			/* Performance Monitor Control */
+	u8 res_104[0xfd0 - 0x104];
+	u32 pid[8];			/* Peripheral ID */
+	u32 cid[4];			/* Component ID */
+	struct {
+		u32 snoop_ctrl;		/* Snoop Control */
+		u32 sha_ord;		/* Shareable Override */
+		u8 res_1008[0x1100 - 0x1008];
+		u32 rc_qos_ord;		/* read channel QoS Value Override */
+		u32 wc_qos_ord;		/* read channel QoS Value Override */
+		u8 res_1108[0x110c - 0x1108];
+		u32 qos_ctrl;		/* QoS Control */
+		u32 max_ot;		/* Max OT */
+		u8 res_1114[0x1130 - 0x1114];
+		u32 target_lat;		/* Target Latency */
+		u32 latency_regu;	/* Latency Regulation */
+		u32 qos_range;		/* QoS Range */
+		u8 res_113c[0x2000 - 0x113c];
+	} slave[5];			/* Slave Interface */
+	u8 res_6000[0x9004 - 0x6000];
+	u32 cycle_counter;		/* Cycle counter */
+	u32 count_ctrl;			/* Count Control */
+	u32 overflow_status;		/* Overflow Flag Status */
+	u8 res_9010[0xa000 - 0x9010];
+	struct {
+		u32 event_select;	/* Event Select */
+		u32 event_count;	/* Event Count */
+		u32 counter_ctrl;	/* Counter Control */
+		u32 overflow_status;	/* Overflow Flag Status */
+		u8 res_a010[0xb000 - 0xa010];
+	} pcounter[4];			/* Performance Counter */
+	u8 res_e004[0x10000 - 0xe004];
+};
+
+/* MMU 500 */
+#define SMMU_SCR0			(SMMU_BASE + 0x0)
+#define SMMU_SCR1			(SMMU_BASE + 0x4)
+#define SMMU_SCR2			(SMMU_BASE + 0x8)
+#define SMMU_SACR			(SMMU_BASE + 0x10)
+#define SMMU_IDR0			(SMMU_BASE + 0x20)
+#define SMMU_IDR1			(SMMU_BASE + 0x24)
+
+#define SMMU_NSCR0			(SMMU_BASE + 0x400)
+#define SMMU_NSCR2			(SMMU_BASE + 0x408)
+#define SMMU_NSACR			(SMMU_BASE + 0x410)
+
+#define SCR0_CLIENTPD_MASK		0x00000001
+#define SCR0_USFCFG_MASK		0x00000400
+
+#endif	/* __ARCH_FSL_LSCH2_IMMAP_H__*/
diff --git a/arch/arm/include/asm/arch-fsl-lsch2/imx-regs.h b/arch/arm/include/asm/arch-fsl-lsch2/imx-regs.h
new file mode 100644
index 0000000..6fdff02
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-lsch2/imx-regs.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#ifndef __ASM_ARCH_FSL_LSCH2_IMX_REGS_H__
+#define __ASM_ARCH_FSL_LSCH2_IMX_REGS_H__
+
+#define I2C_QUIRK_REG	/* enable 8-bit driver */
+#ifdef CONFIG_LPUART_32B_REG
+struct lpuart_fsl {
+	u32 baud;
+	u32 stat;
+	u32 ctrl;
+	u32 data;
+	u32 match;
+	u32 modir;
+	u32 fifo;
+	u32 water;
+};
+#else
+struct lpuart_fsl {
+	u8 ubdh;
+	u8 ubdl;
+	u8 uc1;
+	u8 uc2;
+	u8 us1;
+	u8 us2;
+	u8 uc3;
+	u8 ud;
+	u8 uma1;
+	u8 uma2;
+	u8 uc4;
+	u8 uc5;
+	u8 ued;
+	u8 umodem;
+	u8 uir;
+	u8 reserved;
+	u8 upfifo;
+	u8 ucfifo;
+	u8 usfifo;
+	u8 utwfifo;
+	u8 utcfifo;
+	u8 urwfifo;
+	u8 urcfifo;
+	u8 rsvd[28];
+};
+#endif
+
+#endif /* __ASM_ARCH_FSL_LSCH2_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-fsl-lsch2/mmu.h b/arch/arm/include/asm/arch-fsl-lsch2/mmu.h
new file mode 100644
index 0000000..d1d3481
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-lsch2/mmu.h
@@ -0,0 +1,10 @@
+/*
+ * Copyright 2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_FSL_LSCH2_MMU_H_
+#define _ASM_ARMV8_FSL_LSCH2_MMU_H_
+#include <asm/arch-armv8/mmu.h>
+#endif /* _ASM_ARMV8_FSL_LSCH2_MMU_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-lsch2/ns_access.h b/arch/arm/include/asm/arch-fsl-lsch2/ns_access.h
new file mode 100644
index 0000000..a3ccdb0
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-lsch2/ns_access.h
@@ -0,0 +1,158 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_NS_ACCESS_H_
+#define __FSL_NS_ACCESS_H_
+
+enum csu_cslx_ind {
+	CSU_CSLX_PCIE2_IO = 0,
+	CSU_CSLX_PCIE1_IO,
+	CSU_CSLX_MG2TPR_IP,
+	CSU_CSLX_IFC_MEM,
+	CSU_CSLX_OCRAM,
+	CSU_CSLX_GIC,
+	CSU_CSLX_PCIE1,
+	CSU_CSLX_OCRAM2,
+	CSU_CSLX_QSPI_MEM,
+	CSU_CSLX_PCIE2,
+	CSU_CSLX_SATA,
+	CSU_CSLX_USB1,
+	CSU_CSLX_QM_BM_SWPORTAL,
+	CSU_CSLX_PCIE3 = 16,
+	CSU_CSLX_PCIE3_IO,
+	CSU_CSLX_USB3 = 20,
+	CSU_CSLX_USB2,
+	CSU_CSLX_SERDES = 32,
+	CSU_CSLX_QDMA,
+	CSU_CSLX_LPUART2,
+	CSU_CSLX_LPUART1,
+	CSU_CSLX_LPUART4,
+	CSU_CSLX_LPUART3,
+	CSU_CSLX_LPUART6,
+	CSU_CSLX_LPUART5,
+	CSU_CSLX_DSPI1 = 41,
+	CSU_CSLX_QSPI,
+	CSU_CSLX_ESDHC,
+	CSU_CSLX_IFC = 45,
+	CSU_CSLX_I2C1,
+	CSU_CSLX_I2C3 = 48,
+	CSU_CSLX_I2C2,
+	CSU_CSLX_DUART2 = 50,
+	CSU_CSLX_DUART1,
+	CSU_CSLX_WDT2,
+	CSU_CSLX_WDT1,
+	CSU_CSLX_EDMA,
+	CSU_CSLX_SYS_CNT,
+	CSU_CSLX_DMA_MUX2,
+	CSU_CSLX_DMA_MUX1,
+	CSU_CSLX_DDR,
+	CSU_CSLX_QUICC,
+	CSU_CSLX_DCFG_CCU_RCPM = 60,
+	CSU_CSLX_SECURE_BOOTROM,
+	CSU_CSLX_SFP,
+	CSU_CSLX_TMU,
+	CSU_CSLX_SECURE_MONITOR,
+	CSU_CSLX_SCFG,
+	CSU_CSLX_FM = 66,
+	CSU_CSLX_SEC5_5,
+	CSU_CSLX_BM,
+	CSU_CSLX_QM,
+	CSU_CSLX_GPIO2 = 70,
+	CSU_CSLX_GPIO1,
+	CSU_CSLX_GPIO4,
+	CSU_CSLX_GPIO3,
+	CSU_CSLX_PLATFORM_CONT,
+	CSU_CSLX_CSU,
+	CSU_CSLX_IIC4 = 77,
+	CSU_CSLX_WDT4,
+	CSU_CSLX_WDT3,
+	CSU_CSLX_WDT5 = 81,
+	CSU_CSLX_FTM2 = 86,
+	CSU_CSLX_FTM1,
+	CSU_CSLX_FTM4,
+	CSU_CSLX_FTM3,
+	CSU_CSLX_FTM6 = 90,
+	CSU_CSLX_FTM5,
+	CSU_CSLX_FTM8,
+	CSU_CSLX_FTM7,
+	CSU_CSLX_DSCR = 121,
+};
+
+static struct csu_ns_dev ns_dev[] = {
+	 {CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
+	 {CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
+	 {CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
+	 {CSU_CSLX_IFC_MEM, CSU_ALL_RW},
+	 {CSU_CSLX_OCRAM, CSU_ALL_RW},
+	 {CSU_CSLX_GIC, CSU_ALL_RW},
+	 {CSU_CSLX_PCIE1, CSU_ALL_RW},
+	 {CSU_CSLX_OCRAM2, CSU_ALL_RW},
+	 {CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
+	 {CSU_CSLX_PCIE2, CSU_ALL_RW},
+	 {CSU_CSLX_SATA, CSU_ALL_RW},
+	 {CSU_CSLX_USB1, CSU_ALL_RW},
+	 {CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW},
+	 {CSU_CSLX_PCIE3, CSU_ALL_RW},
+	 {CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
+	 {CSU_CSLX_USB3, CSU_ALL_RW},
+	 {CSU_CSLX_USB2, CSU_ALL_RW},
+	 {CSU_CSLX_SERDES, CSU_ALL_RW},
+	 {CSU_CSLX_QDMA, CSU_ALL_RW},
+	 {CSU_CSLX_LPUART2, CSU_ALL_RW},
+	 {CSU_CSLX_LPUART1, CSU_ALL_RW},
+	 {CSU_CSLX_LPUART4, CSU_ALL_RW},
+	 {CSU_CSLX_LPUART3, CSU_ALL_RW},
+	 {CSU_CSLX_LPUART6, CSU_ALL_RW},
+	 {CSU_CSLX_LPUART5, CSU_ALL_RW},
+	 {CSU_CSLX_DSPI1, CSU_ALL_RW},
+	 {CSU_CSLX_QSPI, CSU_ALL_RW},
+	 {CSU_CSLX_ESDHC, CSU_ALL_RW},
+	 {CSU_CSLX_IFC, CSU_ALL_RW},
+	 {CSU_CSLX_I2C1, CSU_ALL_RW},
+	 {CSU_CSLX_I2C3, CSU_ALL_RW},
+	 {CSU_CSLX_I2C2, CSU_ALL_RW},
+	 {CSU_CSLX_DUART2, CSU_ALL_RW},
+	 {CSU_CSLX_DUART1, CSU_ALL_RW},
+	 {CSU_CSLX_WDT2, CSU_ALL_RW},
+	 {CSU_CSLX_WDT1, CSU_ALL_RW},
+	 {CSU_CSLX_EDMA, CSU_ALL_RW},
+	 {CSU_CSLX_SYS_CNT, CSU_ALL_RW},
+	 {CSU_CSLX_DMA_MUX2, CSU_ALL_RW},
+	 {CSU_CSLX_DMA_MUX1, CSU_ALL_RW},
+	 {CSU_CSLX_DDR, CSU_ALL_RW},
+	 {CSU_CSLX_QUICC, CSU_ALL_RW},
+	 {CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW},
+	 {CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW},
+	 {CSU_CSLX_SFP, CSU_ALL_RW},
+	 {CSU_CSLX_TMU, CSU_ALL_RW},
+	 {CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW},
+	 {CSU_CSLX_SCFG, CSU_ALL_RW},
+	 {CSU_CSLX_FM, CSU_ALL_RW},
+	 {CSU_CSLX_SEC5_5, CSU_ALL_RW},
+	 {CSU_CSLX_BM, CSU_ALL_RW},
+	 {CSU_CSLX_QM, CSU_ALL_RW},
+	 {CSU_CSLX_GPIO2, CSU_ALL_RW},
+	 {CSU_CSLX_GPIO1, CSU_ALL_RW},
+	 {CSU_CSLX_GPIO4, CSU_ALL_RW},
+	 {CSU_CSLX_GPIO3, CSU_ALL_RW},
+	 {CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW},
+	 {CSU_CSLX_CSU, CSU_ALL_RW},
+	 {CSU_CSLX_IIC4, CSU_ALL_RW},
+	 {CSU_CSLX_WDT4, CSU_ALL_RW},
+	 {CSU_CSLX_WDT3, CSU_ALL_RW},
+	 {CSU_CSLX_WDT5, CSU_ALL_RW},
+	 {CSU_CSLX_FTM2, CSU_ALL_RW},
+	 {CSU_CSLX_FTM1, CSU_ALL_RW},
+	 {CSU_CSLX_FTM4, CSU_ALL_RW},
+	 {CSU_CSLX_FTM3, CSU_ALL_RW},
+	 {CSU_CSLX_FTM6, CSU_ALL_RW},
+	 {CSU_CSLX_FTM5, CSU_ALL_RW},
+	 {CSU_CSLX_FTM8, CSU_ALL_RW},
+	 {CSU_CSLX_FTM7, CSU_ALL_RW},
+	 {CSU_CSLX_DSCR, CSU_ALL_RW},
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-fsl-lsch2/soc.h b/arch/arm/include/asm/arch-fsl-lsch2/soc.h
new file mode 100644
index 0000000..73f7de5
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-lsch2/soc.h
@@ -0,0 +1,7 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+void fsl_lsch2_early_init_f(void);
diff --git a/arch/arm/include/asm/arch-fsl-lsch2/spl.h b/arch/arm/include/asm/arch-fsl-lsch2/spl.h
new file mode 100644
index 0000000..356a338
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-lsch2/spl.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_SPL_H__
+#define __ASM_ARCH_SPL_H__
+
+#define BOOT_DEVICE_NONE	0
+#define BOOT_DEVICE_XIP         1
+#define BOOT_DEVICE_XIPWAIT     2
+#define BOOT_DEVICE_NAND	3
+#define BOOT_DEVICE_ONENAND	4
+#define BOOT_DEVICE_MMC1	5
+#define BOOT_DEVICE_MMC2	6
+#define BOOT_DEVICE_MMC2_2	7
+#define BOOT_DEVICE_SPI		10
+
+#endif	/* __ASM_ARCH_SPL_H__ */
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 0c928d4..50e3a83 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -65,6 +65,7 @@
 /*
  * Section
  */
+#define PMD_SECT_NS		(1 << 5)
 #define PMD_SECT_NON_SHARE	(0 << 8)
 #define PMD_SECT_OUTER_SHARE	(2 << 8)
 #define PMD_SECT_INNER_SHARE	(3 << 8)
diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h
index 22fff02..bca9814 100644
--- a/arch/arm/include/asm/config.h
+++ b/arch/arm/include/asm/config.h
@@ -18,6 +18,9 @@
 #ifdef CONFIG_FSL_LSCH3
 #include <asm/arch-fsl-lsch3/config.h>
 #endif
+#ifdef CONFIG_FSL_LSCH2
+#include <asm/arch-fsl-lsch2/config.h>
+#endif
 
 #if defined(CONFIG_LS102XA) || \
 	defined(CONFIG_CPU_PXA27X) || \
diff --git a/include/common.h b/include/common.h
index c12f402..6d92988 100644
--- a/include/common.h
+++ b/include/common.h
@@ -76,6 +76,9 @@ typedef volatile unsigned char	vu_char;
 #ifdef CONFIG_SOC_DA8XX
 #include <asm/arch/hardware.h>
 #endif
+#ifdef CONFIG_LS1043A
+#include <asm/arch-fsl-lsch2/immap_lsch2.h>
+#endif
 
 #include <part.h>
 #include <flash.h>
-- 
2.1.0.27.g96db324

^ permalink raw reply related	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 10/16] ARMv8/ls1043ardb: Add LS1043ARDB board support
  2015-09-17  7:06 [U-Boot] [Patch v2 04/16] net/fm: bug fix when CONFIG_PHYLIB not defined Gong Qianyu
                   ` (4 preceding siblings ...)
  2015-09-17  7:06 ` [U-Boot] [Patch v2 09/16] ARMv8/FSL_LSCH2: Add FSL_LSCH2 SoC Gong Qianyu
@ 2015-09-17  7:06 ` Gong Qianyu
  2015-09-21 17:27   ` York Sun
  2015-09-17  7:06 ` [U-Boot] [Patch v2 11/16] armv8/ls1043ardb: Add nand boot support Gong Qianyu
                   ` (5 subsequent siblings)
  11 siblings, 1 reply; 33+ messages in thread
From: Gong Qianyu @ 2015-09-17  7:06 UTC (permalink / raw)
  To: u-boot

From: Mingkai Hu <Mingkai.Hu@freescale.com>

LS1043ARDB Specification:
-------------------------
Memory subsystem:
 * 2GByte DDR4 SDRAM (32bit but)
 * 128 Mbyte NOR flash single-chip memory
 * 512 Mbyte NAND flash
 * 16 Mbyte high-speed SPI memory
 * SD connector to interface with the SD memory card

Ethernet:
 * XFI 10G port
 * QSGMII with 4x 1G ports
 * Two RGMII ports

PCIe:
 * PCIe2 (Lanes C) to mini-PCIe slot
 * PCIe3 (Lanes D) to PCIe slot

USB 3.0: two super speed USB 3.0 type A ports

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
---
 V2:
 Replaced ns_access.h with fsl_csu.h.
 
 arch/arm/Kconfig                        |   7 ++
 board/freescale/ls1043ardb/Kconfig      |  16 +++
 board/freescale/ls1043ardb/MAINTAINERS  |   7 ++
 board/freescale/ls1043ardb/Makefile     |   9 ++
 board/freescale/ls1043ardb/README       |  87 +++++++++++++++
 board/freescale/ls1043ardb/cpld.c       | 115 +++++++++++++++++++
 board/freescale/ls1043ardb/cpld.h       |  43 +++++++
 board/freescale/ls1043ardb/ddr.c        | 190 +++++++++++++++++++++++++++++++
 board/freescale/ls1043ardb/ddr.h        |  45 ++++++++
 board/freescale/ls1043ardb/ls1043ardb.c | 134 ++++++++++++++++++++++
 configs/ls1043ardb_defconfig            |   3 +
 drivers/i2c/mxc_i2c.c                   |   2 +-
 include/configs/ls1043a_common.h        | 131 ++++++++++++++++++++++
 include/configs/ls1043ardb.h            | 191 ++++++++++++++++++++++++++++++++
 14 files changed, 979 insertions(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8085a24..bc478f7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -662,6 +662,12 @@ config TARGET_LS1021ATWR
 	select CPU_V7
 	select SUPPORT_SPL
 
+config TARGET_LS1043ARDB
+	bool "Support ls1043ardb"
+	select ARM64
+	help
+	  Support for Freescale LS1043ARDB platform.
+
 config TARGET_BALLOON3
 	bool "Support balloon3"
 	select CPU_PXA
@@ -827,6 +833,7 @@ source "board/freescale/ls2085aqds/Kconfig"
 source "board/freescale/ls2085ardb/Kconfig"
 source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
+source "board/freescale/ls1043ardb/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
diff --git a/board/freescale/ls1043ardb/Kconfig b/board/freescale/ls1043ardb/Kconfig
new file mode 100644
index 0000000..eb6a12a
--- /dev/null
+++ b/board/freescale/ls1043ardb/Kconfig
@@ -0,0 +1,16 @@
+
+if TARGET_LS1043ARDB
+
+config SYS_BOARD
+	default "ls1043ardb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-lsch2"
+
+config SYS_CONFIG_NAME
+	default "ls1043ardb"
+
+endif
diff --git a/board/freescale/ls1043ardb/MAINTAINERS b/board/freescale/ls1043ardb/MAINTAINERS
new file mode 100644
index 0000000..b8f6be2
--- /dev/null
+++ b/board/freescale/ls1043ardb/MAINTAINERS
@@ -0,0 +1,7 @@
+LS1043A BOARD
+M:	Mingkai Hu <Mingkai.hu@freescale.com>
+S:	Maintained
+F:	board/freescale/ls1043ardb/
+F:	board/freescale/ls1043ardb/ls1043ardb.c
+F:	include/configs/ls1043ardb.h
+F:	configs/ls1043ardb_defconfig
diff --git a/board/freescale/ls1043ardb/Makefile b/board/freescale/ls1043ardb/Makefile
new file mode 100644
index 0000000..dd17e2e
--- /dev/null
+++ b/board/freescale/ls1043ardb/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright 2015 Freescale Semiconductor
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += cpld.o
+obj-y += ddr.o
+obj-y += ls1043ardb.o
diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README
new file mode 100644
index 0000000..0556e73
--- /dev/null
+++ b/board/freescale/ls1043ardb/README
@@ -0,0 +1,87 @@
+Overview
+--------
+The LS1043A Reference Design Board (RDB) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS1043A
+LayerScape Architecture processor. The LS1043ARDB provides SW development
+platform for the Freescale LS1043A processor series, with a complete
+debugging environment. The LS1043A RDB is lead-free and RoHS-compliant.
+
+LS1043A SoC Overview
+--------------------
+The LS1043A integrated multicore processor combines four ARM Cortex-A53
+processor cores with datapath acceleration optimized for L2/3 packet
+processing, single pass security offload and robust traffic management
+and quality of service.
+
+The LS1043A SoC includes the following function and features:
+ - Four 64-bit ARM Cortex-A53 CPUs
+ - 1 MB unified L2 Cache
+ - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
+   support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
+   the following functions:
+   - Packet parsing, classification, and distribution (FMan)
+   - Queue management for scheduling, packet sequencing, and congestion
+     management (QMan)
+   - Hardware buffer management for buffer allocation and de-allocation (BMan)
+   - Cryptography acceleration (SEC)
+ - Ethernet interfaces by FMan
+   - Up to 1 x XFI supporting 10G interface
+   - Up to 1 x QSGMII
+   - Up to 4 x SGMII supporting 1000Mbps
+   - Up to 2 x SGMII supporting 2500Mbps
+   - Up to 2 x RGMII supporting 1000Mbps
+ - High-speed peripheral interfaces
+   - Three PCIe 2.0 controllers, one supporting x4 operation
+   - One serial ATA (SATA 3.0) controllers
+ - Additional peripheral interfaces
+   - Three high-speed USB 3.0 controllers with integrated PHY
+   - Enhanced secure digital host controller (eSDXC/eMMC)
+   - Quad Serial Peripheral Interface (QSPI) Controller
+   - Serial peripheral interface (SPI) controller
+   - Four I2C controllers
+   - Two DUARTs
+   - Integrated flash controller supporting NAND and NOR flash
+ - QorIQ platform's trust architecture 2.1
+
+ LS1043ARDB board Overview
+ -----------------------
+ - SERDES Connections, 4 lanes supporting:
+      - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and
+        standard PCIe card
+      - QSGMII with x4 RJ45 connector
+      - XFI with x1 RJ45 connector
+ - DDR Controller
+     - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s
+ -IFC/Local Bus
+    - One 128MB NOR flash 16-bit data bus
+    - One 512 MB NAND flash with ECC support
+    - CPLD connection
+ - USB 3.0
+    - Two super speed USB 3.0 Type A ports
+ - SDHC: connects directly to a full SD/MMC slot
+ - DSPI: 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
+ - 4 I2C controllers
+ - UART
+   - Two 4-pin serial ports at up to 115.2 Kbit/s
+   - Two DB9 D-Type connectors supporting one Serial port each
+ - ARM JTAG support
+
+Memory map from core's view
+----------------------------
+Start Address	End Address	Description		Size
+0x00_0000_0000	0x00_000F_FFFF	Secure Boot ROM		1MB
+0x00_0100_0000	0x00_0FFF_FFFF	CCSRBAR			240MB
+0x00_1000_0000	0x00_1000_FFFF	OCRAM0			64KB
+0x00_1001_0000	0x00_1001_FFFF	OCRAM1			64KB
+0x00_2000_0000	0x00_20FF_FFFF	DCSR			16MB
+0x00_6000_0000	0x00_67FF_FFFF	IFC - NOR Flash		128MB
+0x00_7E80_0000	0x00_7E80_FFFF	IFC - NAND Flash	64KB
+0x00_7FB0_0000	0x00_7FB0_0FFF	IFC - FPGA		4KB
+0x00_8000_0000	0x00_FFFF_FFFF	DRAM1			2GB
+
+Booting Options
+---------------
+a) NOR boot
+b) NAND boot
+c) SD boot
diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c
new file mode 100644
index 0000000..3f1101e
--- /dev/null
+++ b/board/freescale/ls1043ardb/cpld.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Freescale LS1043ARDB board-specific CPLD controlling supports.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include "cpld.h"
+
+u8 cpld_read(unsigned int reg)
+{
+	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+	return in_8(p + reg);
+}
+
+void cpld_write(unsigned int reg, u8 value)
+{
+	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+	out_8(p + reg, value);
+}
+
+/* Set the boot bank to the alternate bank */
+void cpld_set_altbank(void)
+{
+	u8 reg4 = CPLD_READ(soft_mux_on);
+	u8 reg7 = CPLD_READ(vbank);
+
+	CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL);
+
+	reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
+	CPLD_WRITE(vbank, reg7);
+
+	CPLD_WRITE(system_rst, 1);
+}
+
+/* Set the boot bank to the default bank */
+void cpld_set_defbank(void)
+{
+	CPLD_WRITE(global_rst, 1);
+}
+
+#ifdef DEBUG
+static void cpld_dump_regs(void)
+{
+	printf("cpld_ver	= %x\n", CPLD_READ(cpld_ver));
+	printf("cpld_ver_sub	= %x\n", CPLD_READ(cpld_ver_sub));
+	printf("pcba_ver	= %x\n", CPLD_READ(pcba_ver));
+	printf("soft_mux_on	= %x\n", CPLD_READ(soft_mux_on));
+	printf("cfg_rcw_src1	= %x\n", CPLD_READ(cfg_rcw_src1));
+	printf("cfg_rcw_src2	= %x\n", CPLD_READ(cfg_rcw_src2));
+	printf("vbank		= %x\n", CPLD_READ(vbank));
+	printf("sysclk_sel	= %x\n", CPLD_READ(sysclk_sel));
+	printf("uart_sel	= %x\n", CPLD_READ(uart_sel));
+	printf("sd1refclk_sel	= %x\n", CPLD_READ(sd1refclk_sel));
+	printf("tdmclk_mux_sel	= %x\n", CPLD_READ(tdmclk_mux_sel));
+	printf("sdhc_spics_sel	= %x\n", CPLD_READ(sdhc_spics_sel));
+	printf("status_led	= %x\n", CPLD_READ(status_led));
+	putc('\n');
+}
+#endif
+
+void cpld_rev_bit(unsigned char *value)
+{
+	u8 rev_val, val;
+	int i;
+
+	val = *value;
+	rev_val = val & 1;
+	for (i = 1; i <= 7; i++) {
+		val >>= 1;
+		rev_val <<= 1;
+		rev_val |= val & 1;
+	}
+
+	*value = rev_val;
+}
+
+int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int rc = 0;
+
+	if (argc <= 1)
+		return cmd_usage(cmdtp);
+
+	if (strcmp(argv[1], "reset") == 0) {
+		if (strcmp(argv[2], "altbank") == 0)
+			cpld_set_altbank();
+		else
+			cpld_set_defbank();
+#ifdef DEBUG
+	} else if (strcmp(argv[1], "dump") == 0) {
+		cpld_dump_regs();
+#endif
+	} else {
+		rc = cmd_usage(cmdtp);
+	}
+
+	return rc;
+}
+
+U_BOOT_CMD(
+	cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
+	"Reset the board or alternate bank",
+	"reset: reset to default bank\n"
+	"cpld reset altbank: reset to alternate bank\n"
+#ifdef DEBUG
+	"cpld dump - display the CPLD registers\n"
+#endif
+);
diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h
new file mode 100644
index 0000000..ea4efd8
--- /dev/null
+++ b/board/freescale/ls1043ardb/cpld.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CPLD_H__
+#define __CPLD_H__
+
+/*
+ * CPLD register set of LS1043ARDB board-specific.
+ */
+struct cpld_data {
+	u8 cpld_ver;		/* 0x0 - CPLD Major Revision Register */
+	u8 cpld_ver_sub;	/* 0x1 - CPLD Minor Revision Register */
+	u8 pcba_ver;		/* 0x2 - PCBA Revision Register */
+	u8 system_rst;		/* 0x3 - system reset register */
+	u8 soft_mux_on;		/* 0x4 - Switch Control Enable Register */
+	u8 cfg_rcw_src1;	/* 0x5 - Reset config word 1 */
+	u8 cfg_rcw_src2;	/* 0x6 - Reset config word 1 */
+	u8 vbank;		/* 0x7 - Flash bank selection Control */
+	u8 sysclk_sel;		/* 0x8 - */
+	u8 uart_sel;		/* 0x9 - */
+	u8 sd1refclk_sel;	/* 0xA - */
+	u8 tdmclk_mux_sel;	/* 0xB - */
+	u8 sdhc_spics_sel;	/* 0xC - */
+	u8 status_led;		/* 0xD - */
+	u8 global_rst;		/* 0xE - */
+};
+
+u8 cpld_read(unsigned int reg);
+void cpld_write(unsigned int reg, u8 value);
+void cpld_rev_bit(unsigned char *value);
+
+#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
+#define CPLD_WRITE(reg, value)  \
+	cpld_write(offsetof(struct cpld_data, reg), value)
+
+/* CPLD on IFC */
+#define CPLD_SW_MUX_BANK_SEL	0x40
+#define CPLD_BANK_SEL_MASK	0x07
+#define CPLD_BANK_SEL_ALTBANK	0x04
+#endif
diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c
new file mode 100644
index 0000000..7bb1fa8
--- /dev/null
+++ b/board/freescale/ls1043ardb/ddr.c
@@ -0,0 +1,190 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include "ddr.h"
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include <fsl_sleep.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+			   dimm_params_t *pdimm,
+			   unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num > 1) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	pbsp = udimms[0];
+
+	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				popts->cpo_override = pbsp->cpo_override;
+				popts->write_data_delay =
+					pbsp->write_data_delay;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found for %lu MT/s\n",
+		       ddr_freq);
+		printf("Trying to use the highest speed (%u) parameters\n",
+		       pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
+	      pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
+
+	/* force DDR bus width to 32 bits */
+	popts->data_bus_width = 1;
+	popts->otf_burst_chop_en = 0;
+	popts->burst_length = DDR_BL8;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 1;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+			  DDR_CDR2_VREF_OVRD(70);	/* Vref = 70% */
+}
+
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 1,
+	.rank_density = 2147483648u,
+	.capacity = 2147483648u,
+	.primary_sdram_width = 32,
+	.ec_sdram_width = 0,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 15,
+	.n_col_addr = 10,
+	.bank_addr_bits = 0,
+	.bank_group_bits = 2,
+	.edc_config = 0,
+	.burst_lengths_bitmask = 0x0c,
+
+	.tckmin_x_ps = 938,
+	.tckmax_ps = 1500,
+	.caslat_x = 0x000DFA00,
+	.taa_ps = 13500,
+	.trcd_ps = 13500,
+	.trp_ps = 13500,
+	.tras_ps = 33000,
+	.trc_ps = 46500,
+	.trfc1_ps = 260000,
+	.trfc2_ps = 160000,
+	.trfc4_ps = 110000,
+	.tfaw_ps = 21000,
+	.trrds_ps = 3700,
+	.trrdl_ps = 5300,
+	.tccdl_ps = 5355,
+	.refresh_rate_ps = 7800000,
+	.dq_mapping[0] = 0x0,
+	.dq_mapping[1] = 0x0,
+	.dq_mapping[2] = 0x0,
+	.dq_mapping[3] = 0x0,
+	.dq_mapping[4] = 0x0,
+	.dq_mapping[5] = 0x0,
+	.dq_mapping[6] = 0x0,
+	.dq_mapping[7] = 0x0,
+	.dq_mapping[8] = 0x0,
+	.dq_mapping[9] = 0x0,
+	.dq_mapping[10] = 0x0,
+	.dq_mapping[11] = 0x0,
+	.dq_mapping[12] = 0x0,
+	.dq_mapping[13] = 0x0,
+	.dq_mapping[14] = 0x0,
+	.dq_mapping[15] = 0x0,
+	.dq_mapping[16] = 0x0,
+	.dq_mapping[17] = 0x0,
+	.dq_mapping_ors = 0,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+			    unsigned int controller_number,
+			    unsigned int dimm_number)
+{
+	static const char dimm_model[] = "Fixed DDR on board";
+
+	if (((controller_number == 0) && (dimm_number == 0)) ||
+	    ((controller_number == 1) && (dimm_number == 0))) {
+		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+	}
+
+	return 0;
+}
+#endif
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size;
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
+	puts("Initializing DDR....\n");
+	dram_size = fsl_ddr_sdram();
+#else
+	dram_size =  fsl_ddr_sdram_size();
+#endif
+#ifdef CONFIG_FSL_DEEP_SLEEP
+	fsl_dp_ddr_restore();
+#endif
+
+	return dram_size;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+}
diff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h
new file mode 100644
index 0000000..b17eb80
--- /dev/null
+++ b/board/freescale/ls1043ardb/ddr.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+	u32 cpo_override;
+	u32 write_data_delay;
+	u32 force_2t;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
+	 */
+#ifdef CONFIG_SYS_FSL_DDR4
+	{1,  1666, 0, 6,     7, 0x07090800, 0x00000000,},
+	{1,  1900, 0, 6,     7, 0x07090800, 0x00000000,},
+	{1,  2200, 0, 6,     7, 0x07090800, 0x00000000,},
+#endif
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+
+#endif
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
new file mode 100644
index 0000000..076881c
--- /dev/null
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch-fsl-lsch2/immap_lsch2.h>
+#include <asm/arch-fsl-lsch2/soc.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <hwconfig.h>
+#include <ahci.h>
+#include <scsi.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <fsl_ifc.h>
+#include "cpld.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
+	u8 cfg_rcw_src1, cfg_rcw_src2;
+	u32 cfg_rcw_src;
+	u32 sd1refclk_sel;
+
+	printf("Board: LS1043ARDB, boot from ");
+
+	cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
+	cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
+	cpld_rev_bit(&cfg_rcw_src1);
+	cfg_rcw_src = cfg_rcw_src1;
+	cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
+
+	if (cfg_rcw_src == 0x25)
+		printf("vBank %d\n", CPLD_READ(vbank));
+	else if (cfg_rcw_src == 0x106)
+		puts("NAND\n");
+	else
+		printf("Invalid setting of SW4\n");
+
+	printf("CPLD:  V%x.%x\nPCBA:  V%x.0\n", CPLD_READ(cpld_ver),
+	       CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
+
+	puts("SERDES Reference Clocks:\n");
+	sd1refclk_sel = CPLD_READ(sd1refclk_sel);
+	printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = initdram(0);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+	return 0;
+}
+
+int board_init(void)
+{
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+
+	/*
+	 * Set CCI-400 control override register to enable barrier
+	 * transaction
+	 */
+	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_FSL_IFC
+	init_final_memctl_regs();
+#endif
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+	/*
+	 * Configure SMMU3 to make transactions with CAAM stream ID
+	 * as cacheable
+	 */
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+
+	return 0;
+}
+
+int config_board_mux(void)
+{
+	return 0;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+	config_board_mux();
+
+	return 0;
+}
+#endif
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	return 0;
+}
+
+u8 flash_read8(void *addr)
+{
+	return __raw_readb(addr + 1);
+}
+
+void flash_write16(u16 val, void *addr)
+{
+	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
+
+	__raw_writew(shftval, addr);
+}
+
+u16 flash_read16(void *addr)
+{
+	u16 val = __raw_readw(addr);
+
+	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
+}
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
new file mode 100644
index 0000000..62a96aa
--- /dev/null
+++ b/configs/ls1043ardb_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043ARDB=y
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index f1056e2..2c84847 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -524,7 +524,7 @@ static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
 
 static struct mxc_i2c_bus mxc_i2c_buses[] = {
 #if defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LSCH3) || \
-		defined(CONFIG_VF610)
+		defined(CONFIG_VF610) || defined(CONFIG_FSL_LSCH2)
 	{ 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
 	{ 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
 	{ 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
new file mode 100644
index 0000000..139005c
--- /dev/null
+++ b/include/configs/ls1043a_common.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1043A_COMMON_H
+#define __LS1043A_COMMON_H
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define CONFIG_REMAKE_ELF
+#define CONFIG_FSL_LSCH2
+#define CONFIG_LS1043A
+#define CONFIG_GICV2
+#define CONFIG_FSL_CLK
+
+#include <asm/arch-fsl-lsch2/config.h>
+#ifdef CONFIG_SYS_FSL_SRDS_1
+#define	CONFIG_SYS_HAS_SERDES
+#endif
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F	1
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+#ifndef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_FSL_DDR3		/* Use DDR3 memory */
+#endif
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		25000000	/* 25MHz */
+
+/* CSU */
+#define	CONFIG_LS1043A_NS_ACCESS
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0))
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* IFC */
+#define CONFIG_FSL_IFC
+/*
+ * CONFIG_SYS_FLASH_BASE has the final address (core view)
+ * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
+ * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
+ * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
+ */
+#define CONFIG_SYS_FLASH_BASE			0x60000000
+#define CONFIG_SYS_FLASH_BASE_PHYS		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
+
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
+#endif
+
+/* I2C */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+#define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE		128
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"loadaddr=0x80100000\0"			\
+	"kernel_addr=0x100000\0"		\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"kernel_start=0x61200000\0"		\
+	"kernel_load=0x807f0000\0"		\
+	"kernel_size=0x1000000\0"		\
+	"console=ttyAMA0,38400n8\0"
+
+#define CONFIG_BOOTARGS			"console=ttyS0,115200 root=/dev/ram0 " \
+					"earlycon=uart8250,0x21c0500,115200"
+#define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
+					"$kernel_size && bootm $kernel_load"
+#define CONFIG_BOOTDELAY		10
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING		1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS		64	/* max command args */
+
+#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
+
+#endif /* __LS1043A_COMMON_H */
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
new file mode 100644
index 0000000..1f66201
--- /dev/null
+++ b/include/configs/ls1043ardb.h
@@ -0,0 +1,191 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1043ARDB_H__
+#define __LS1043ARDB_H__
+
+#include "ls1043a_common.h"
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_TEXT_BASE		0x60100000
+
+#define CONFIG_SYS_CLK_FREQ		100000000
+#define CONFIG_DDR_CLK_FREQ		100000000
+
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+/* Physical Memory Map */
+#define CONFIG_CHIP_SELECTS_PER_CTRL	4
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_SPD_BUS_NUM		0
+
+#define CONFIG_FSL_DDR_BIST
+#define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
+#define CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
+
+/*
+ * NOR Flash Definitions
+ */
+#define CONFIG_SYS_NOR_CSPR_EXT		(0x0)
+#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
+#define CONFIG_SYS_NOR_CSPR					\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+					CSOR_NOR_TRHZ_80)
+#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x1) | \
+					FTIM0_NOR_TEADC(0x1) | \
+					FTIM0_NOR_TAVDS(0x0) | \
+					FTIM0_NOR_TEAHC(0xc))
+#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x1c) | \
+					FTIM1_NOR_TRAD_NOR(0xb) | \
+					FTIM1_NOR_TSEQRAD_NOR(0x9))
+#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x1) | \
+					FTIM2_NOR_TCH(0x4) | \
+					FTIM2_NOR_TWPH(0x8) | \
+					FTIM2_NOR_TWP(0x10))
+#define CONFIG_SYS_NOR_FTIM3		0
+#define CONFIG_SYS_IFC_CCR		0x01000000
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }
+
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+
+/*
+ * NAND Flash Definitions
+ */
+#define CONFIG_NAND_FSL_IFC
+
+#define CONFIG_SYS_NAND_BASE		0x7e800000
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8	\
+				| CSPR_MSEL_NAND	\
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x7) | \
+					FTIM0_NAND_TWH(0xa))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0xe)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
+					FTIM2_NAND_TREH(0xa) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+/*
+ * CPLD
+ */
+#define CONFIG_SYS_CPLD_BASE		0x7fb00000
+#define CPLD_BASE_PHYS			CONFIG_SYS_CPLD_BASE
+
+#define CONFIG_SYS_CPLD_CSPR_EXT	(0x0)
+#define CONFIG_SYS_CPLD_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
+					CSPR_PORT_SIZE_8 | \
+					CSPR_MSEL_GPCM | \
+					CSPR_V)
+#define CONFIG_SYS_CPLD_AMASK		IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_CPLD_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+					CSOR_NOR_NOR_MODE_AVD_NOR | \
+					CSOR_NOR_TRHZ_80)
+
+/* CPLD Timing parameters for IFC GPCM */
+#define CONFIG_SYS_CPLD_FTIM0		(FTIM0_GPCM_TACSE(0xf) | \
+					FTIM0_GPCM_TEADC(0xf) | \
+					FTIM0_GPCM_TEAHC(0xf))
+#define CONFIG_SYS_CPLD_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+					FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CPLD_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
+					FTIM2_GPCM_TCH(0xf) | \
+					FTIM2_GPCM_TWP(0xff))
+#define CONFIG_SYS_CPLD_FTIM3		0x0
+
+/* IFC Timing Params */
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_CPLD_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_CPLD_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_CPLD_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_CPLD_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_CPLD_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_CPLD_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_CPLD_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_CPLD_FTIM3
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM		0
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			0x20000
+
+#endif /* __LS1043ARDB_H__ */
-- 
2.1.0.27.g96db324

^ permalink raw reply related	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 11/16] armv8/ls1043ardb: Add nand boot support
  2015-09-17  7:06 [U-Boot] [Patch v2 04/16] net/fm: bug fix when CONFIG_PHYLIB not defined Gong Qianyu
                   ` (5 preceding siblings ...)
  2015-09-17  7:06 ` [U-Boot] [Patch v2 10/16] ARMv8/ls1043ardb: Add LS1043ARDB board support Gong Qianyu
@ 2015-09-17  7:06 ` Gong Qianyu
  2015-09-17 20:16   ` Scott Wood
  2015-09-17  7:06 ` [U-Boot] [Patch v2 12/16] armv8/ls1043ardb: Add cpld command to boot from nand Gong Qianyu
                   ` (4 subsequent siblings)
  11 siblings, 1 reply; 33+ messages in thread
From: Gong Qianyu @ 2015-09-17  7:06 UTC (permalink / raw)
  To: u-boot

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
---
 V2:
 -Removed unecessary NAND_PAGE_SIZE in ls1043a_common.h.
 -Fixed "select SUPPORT_SPL" in arch/arm/Kconfig.
 -Used CONFIG_FSL_IFC instead of SPL_NAND_SUPPORT for init_early_memctl_regs() in spl.c
 -Replaced ns_access.h with fsl_csu.h.

 arch/arm/Kconfig                                   |  1 +
 arch/arm/cpu/armv8/fsl-lsch2/Makefile              |  1 +
 arch/arm/cpu/armv8/fsl-lsch2/spl.c                 | 79 ++++++++++++++++++++++
 arch/arm/include/asm/arch-fsl-lsch2/spl.h          |  2 +-
 board/freescale/ls1043ardb/ls1043ardb_pbi.cfg      | 14 ++++
 board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg |  7 ++
 configs/ls1043ardb_nand_defconfig                  |  4 ++
 include/configs/ls1043a_common.h                   | 30 ++++++++
 include/configs/ls1043ardb.h                       | 40 +++++++++++
 9 files changed, 177 insertions(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bc478f7..f935f19 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -665,6 +665,7 @@ config TARGET_LS1021ATWR
 config TARGET_LS1043ARDB
 	bool "Support ls1043ardb"
 	select ARM64
+	select SUPPORT_SPL
 	help
 	  Support for Freescale LS1043ARDB platform.
 
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/Makefile b/arch/arm/cpu/armv8/fsl-lsch2/Makefile
index 2280ebf..937e3af 100644
--- a/arch/arm/cpu/armv8/fsl-lsch2/Makefile
+++ b/arch/arm/cpu/armv8/fsl-lsch2/Makefile
@@ -10,3 +10,4 @@ obj-y += lowlevel.o
 obj-y += speed.o
 obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o ls1043a_serdes.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_SPL) += spl.o
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/spl.c b/arch/arm/cpu/armv8/fsl-lsch2/spl.c
new file mode 100644
index 0000000..cd667e5
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch2/spl.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <fsl_ifc.h>
+#include <fsl_csu.h>
+#include <i2c.h>
+#include <asm/arch-fsl-lsch2/immap_lsch2.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+#ifdef CONFIG_SPL_SPI_SUPPORT
+	return BOOT_DEVICE_SPI;
+#endif
+#ifdef CONFIG_SPL_MMC_SUPPORT
+	return BOOT_DEVICE_MMC1;
+#endif
+#ifdef CONFIG_SPL_NAND_SUPPORT
+	return BOOT_DEVICE_NAND;
+#endif
+	return 0;
+}
+
+u32 spl_boot_mode(void)
+{
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_MMC1:
+#ifdef CONFIG_SPL_FAT_SUPPORT
+		return MMCSD_MODE_FAT;
+#else
+		return MMCSD_MODE_RAW;
+#endif
+		break;
+	case BOOT_DEVICE_NAND:
+	case BOOT_DEVICE_SPI:
+		return 0;
+		break;
+	default:
+		puts("spl: error: unsupported device\n");
+		hang();
+	}
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+#ifdef CONFIG_FSL_IFC
+	init_early_memctl_regs();
+#endif
+	/* Set global data pointer */
+	gd = &gdata;
+
+	timer_init();
+
+	get_clocks();
+
+	preloader_console_init();
+
+#ifdef CONFIG_SPL_I2C_SUPPORT
+	i2c_init_all();
+#endif
+	dram_init();
+
+	/* Clear the BSS */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+	board_init_r(NULL, 0);
+}
+#endif
diff --git a/arch/arm/include/asm/arch-fsl-lsch2/spl.h b/arch/arm/include/asm/arch-fsl-lsch2/spl.h
index 356a338..11daf9c 100644
--- a/arch/arm/include/asm/arch-fsl-lsch2/spl.h
+++ b/arch/arm/include/asm/arch-fsl-lsch2/spl.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
diff --git a/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg b/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
new file mode 100644
index 0000000..f072274
--- /dev/null
+++ b/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
@@ -0,0 +1,14 @@
+#Configure Scratch register
+09570600 00000000
+09570604 10000000
+#Alt base register
+09570158 00001000
+#Disable CCI barrier tranaction
+09570178 0000e010
+09180000 00000008
+#USB PHY frequency sel
+09570418 0000009e
+0957041c 0000009e
+09570420 0000009e
+#flush PBI data
+096100c0 000fffff
diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
new file mode 100644
index 0000000..935ffc0
--- /dev/null
+++ b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+0810000f 0c000000 00000000 00000000
+14550002 80004012 e0106000 61002000
+00000000 00000000 00000000 00038800
+00000000 00001100 00000096 00000001
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
new file mode 100644
index 0000000..fffaca0
--- /dev/null
+++ b/configs/ls1043ardb_nand_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043ARDB=y
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 139005c..5317976 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -60,6 +60,36 @@
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
+/* NAND SPL */
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SPL_PBL_PAD
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_TEXT_BASE		0x10000000
+#define CONFIG_SPL_MAX_SIZE		0x1a000
+#define CONFIG_SPL_STACK		0x1001d000
+#define CONFIG_SPL_PAD_TO		0x1c000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(640 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
+#define CONFIG_SPL_BSS_START_ADDR	0x80100000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_MONITOR_LEN		0xa0000
+#endif
+
 /* IFC */
 #define CONFIG_FSL_IFC
 /*
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 1f66201..5e6e09d 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -12,7 +12,11 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_SYS_TEXT_BASE		0x82000000
+#else
 #define CONFIG_SYS_TEXT_BASE		0x60100000
+#endif
 
 #define CONFIG_SYS_CLK_FREQ		100000000
 #define CONFIG_DDR_CLK_FREQ		100000000
@@ -33,6 +37,14 @@
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
+#endif
+
 /*
  * NOR Flash Definitions
  */
@@ -144,6 +156,25 @@
 #define CONFIG_SYS_CPLD_FTIM3		0x0
 
 /* IFC Timing Params */
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
@@ -161,6 +192,7 @@
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
 
 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_CPLD_CSPR_EXT
 #define CONFIG_SYS_CSPR2		CONFIG_SYS_CPLD_CSPR
@@ -183,9 +215,17 @@
 /*
  * Environment
  */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
 #define CONFIG_ENV_SECT_SIZE		0x20000
 #define CONFIG_ENV_SIZE			0x20000
+#endif
 
 #endif /* __LS1043ARDB_H__ */
-- 
2.1.0.27.g96db324

^ permalink raw reply related	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 12/16] armv8/ls1043ardb: Add cpld command to boot from nand
  2015-09-17  7:06 [U-Boot] [Patch v2 04/16] net/fm: bug fix when CONFIG_PHYLIB not defined Gong Qianyu
                   ` (6 preceding siblings ...)
  2015-09-17  7:06 ` [U-Boot] [Patch v2 11/16] armv8/ls1043ardb: Add nand boot support Gong Qianyu
@ 2015-09-17  7:06 ` Gong Qianyu
  2015-09-21 17:27   ` York Sun
  2015-09-17  7:06 ` [U-Boot] [Patch v2 13/16] armv8/ls1043a: Add Fman support Gong Qianyu
                   ` (3 subsequent siblings)
  11 siblings, 1 reply; 33+ messages in thread
From: Gong Qianyu @ 2015-09-17  7:06 UTC (permalink / raw)
  To: u-boot

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
---
 board/freescale/ls1043ardb/cpld.c | 18 ++++++++++++++++++
 board/freescale/ls1043ardb/cpld.h |  1 +
 2 files changed, 19 insertions(+)

diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c
index 3f1101e..5acb97d 100644
--- a/board/freescale/ls1043ardb/cpld.c
+++ b/board/freescale/ls1043ardb/cpld.c
@@ -45,6 +45,21 @@ void cpld_set_defbank(void)
 	CPLD_WRITE(global_rst, 1);
 }
 
+void cpld_set_nand(void)
+{
+	u16 reg = CPLD_CFG_RCW_SRC_NAND;
+	u8 reg5 = (u8)(reg >> 1);
+	u8 reg6 = (u8)(reg & 1);
+	cpld_rev_bit(&reg5);
+
+	CPLD_WRITE(soft_mux_on, 1);
+
+	CPLD_WRITE(cfg_rcw_src1, reg5);
+	CPLD_WRITE(cfg_rcw_src2, reg6);
+
+	CPLD_WRITE(system_rst, 1);
+}
+
 #ifdef DEBUG
 static void cpld_dump_regs(void)
 {
@@ -91,6 +106,8 @@ int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	if (strcmp(argv[1], "reset") == 0) {
 		if (strcmp(argv[2], "altbank") == 0)
 			cpld_set_altbank();
+		else if (strcmp(argv[2], "nand") == 0)
+			cpld_set_nand();
 		else
 			cpld_set_defbank();
 #ifdef DEBUG
@@ -109,6 +126,7 @@ U_BOOT_CMD(
 	"Reset the board or alternate bank",
 	"reset: reset to default bank\n"
 	"cpld reset altbank: reset to alternate bank\n"
+	"cpld reset nand: reset to boot from NAND flash\n"
 #ifdef DEBUG
 	"cpld dump - display the CPLD registers\n"
 #endif
diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h
index ea4efd8..5f43a8a 100644
--- a/board/freescale/ls1043ardb/cpld.h
+++ b/board/freescale/ls1043ardb/cpld.h
@@ -40,4 +40,5 @@ void cpld_rev_bit(unsigned char *value);
 #define CPLD_SW_MUX_BANK_SEL	0x40
 #define CPLD_BANK_SEL_MASK	0x07
 #define CPLD_BANK_SEL_ALTBANK	0x04
+#define CPLD_CFG_RCW_SRC_NAND	0x106
 #endif
-- 
2.1.0.27.g96db324

^ permalink raw reply related	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 13/16] armv8/ls1043a: Add Fman support
  2015-09-17  7:06 [U-Boot] [Patch v2 04/16] net/fm: bug fix when CONFIG_PHYLIB not defined Gong Qianyu
                   ` (7 preceding siblings ...)
  2015-09-17  7:06 ` [U-Boot] [Patch v2 12/16] armv8/ls1043ardb: Add cpld command to boot from nand Gong Qianyu
@ 2015-09-17  7:06 ` Gong Qianyu
  2015-09-17  7:06 ` [U-Boot] [Patch v2 14/16] armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardb Gong Qianyu
                   ` (2 subsequent siblings)
  11 siblings, 0 replies; 33+ messages in thread
From: Gong Qianyu @ 2015-09-17  7:06 UTC (permalink / raw)
  To: u-boot

From: Shaohui Xie <Shaohui.Xie@freescale.com>

Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
---
 arch/arm/cpu/armv8/fsl-lsch2/cpu.c      |  19 +++++
 arch/arm/cpu/armv8/fsl-lsch2/fdt.c      |   7 ++
 arch/arm/cpu/armv8/fsl-lsch2/speed.c    |  23 ++++++
 board/freescale/common/fman.c           |   6 +-
 board/freescale/ls1043ardb/Makefile     |   1 +
 board/freescale/ls1043ardb/eth.c        |  77 +++++++++++++++++++++
 board/freescale/ls1043ardb/ls1043ardb.c |   4 ++
 drivers/net/fm/Makefile                 |   1 +
 drivers/net/fm/init.c                   |  10 ++-
 drivers/net/fm/ls1043.c                 | 119 ++++++++++++++++++++++++++++++++
 include/configs/ls1043a_common.h        |  12 ++++
 include/configs/ls1043ardb.h            |  25 +++++++
 12 files changed, 301 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-lsch2/cpu.c b/arch/arm/cpu/armv8/fsl-lsch2/cpu.c
index 1155723..18886ea 100644
--- a/arch/arm/cpu/armv8/fsl-lsch2/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch2/cpu.c
@@ -11,6 +11,7 @@
 #include <asm/io.h>
 #include <asm/arch-fsl-lsch2/immap_lsch2.h>
 #include <asm/arch/fsl_serdes.h>
+#include <fm_eth.h>
 #include "speed.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -358,6 +359,9 @@ int print_cpuinfo(void)
 	printf("\n       Bus:      %-4s MHz  ",
 	       strmhz(buf, sysinfo.freq_systembus));
 	printf("DDR:      %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
+#ifdef CONFIG_SYS_DPAA_FMAN
+	printf("  FMAN:     %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
+#endif
 	puts("\n");
 
 	/*
@@ -378,11 +382,26 @@ int print_cpuinfo(void)
 }
 #endif
 
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+	fm_standard_init(bis);
+#endif
+	return 0;
+}
+
 int arch_early_init_r(void)
 {
 #ifdef CONFIG_SYS_HAS_SERDES
 	fsl_serdes_init();
 #endif
+#ifdef CONFIG_FMAN_ENET
+	fman_enet_init();
+#endif
 	return 0;
 }
 
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/fdt.c b/arch/arm/cpu/armv8/fsl-lsch2/fdt.c
index 015ad76..a646faa 100644
--- a/arch/arm/cpu/armv8/fsl-lsch2/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-lsch2/fdt.c
@@ -7,6 +7,13 @@
 #include <common.h>
 #include <libfdt.h>
 #include <fdt_support.h>
+#include <phy.h>
+
+int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
+{
+	return fdt_setprop_string(blob, offset, "phy-connection-type",
+					 phy_string_for_interface(phyc));
+}
 
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/speed.c b/arch/arm/cpu/armv8/fsl-lsch2/speed.c
index 197cc0e..9ef630a 100644
--- a/arch/arm/cpu/armv8/fsl-lsch2/speed.c
+++ b/arch/arm/cpu/armv8/fsl-lsch2/speed.c
@@ -25,6 +25,9 @@ void get_sys_info(struct sys_info *sys_info)
 	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
 	u32 ccr;
 #endif
+#ifdef CONFIG_SYS_DPAA_FMAN
+	u32 rcw_tmp;
+#endif
 	struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
 	unsigned int cpu;
 	const u8 core_cplx_pll[8] = {
@@ -79,6 +82,26 @@ void get_sys_info(struct sys_info *sys_info)
 
 #define HWA_CGA_M1_CLK_SEL	0xe0000000
 #define HWA_CGA_M1_CLK_SHIFT	29
+#ifdef CONFIG_SYS_DPAA_FMAN
+	rcw_tmp = in_be32(&gur->rcwsr[7]);
+	switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
+	case 2:
+		sys_info->freq_fman[0] = freq_c_pll[0] / 2;
+		break;
+	case 3:
+		sys_info->freq_fman[0] = freq_c_pll[0] / 3;
+		break;
+	case 6:
+		sys_info->freq_fman[0] = freq_c_pll[1] / 2;
+		break;
+	case 7:
+		sys_info->freq_fman[0] = freq_c_pll[1] / 3;
+		break;
+	default:
+		printf("Error: Unknown FMan1 clock select!\n");
+		break;
+	}
+#endif
 
 #define HWA_CGA_M2_CLK_SEL	0x00000007
 #define HWA_CGA_M2_CLK_SHIFT	0
diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c
index 9dc5402..e491064 100644
--- a/board/freescale/common/fman.c
+++ b/board/freescale/common/fman.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011-2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -10,7 +10,11 @@
 #include <fdt_support.h>
 
 #include <fm_eth.h>
+#ifdef CONFIG_FSL_LSCH2
+#include <asm/arch/fsl_serdes.h>
+#else
 #include <asm/fsl_serdes.h>
+#endif
 
 /*
  * Given the following ...
diff --git a/board/freescale/ls1043ardb/Makefile b/board/freescale/ls1043ardb/Makefile
index dd17e2e..5fe1cc9 100644
--- a/board/freescale/ls1043ardb/Makefile
+++ b/board/freescale/ls1043ardb/Makefile
@@ -7,3 +7,4 @@
 obj-y += cpld.o
 obj-y += ddr.o
 obj-y += ls1043ardb.o
+obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c
new file mode 100644
index 0000000..c5e70dd
--- /dev/null
+++ b/board/freescale/ls1043ardb/eth.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <fsl_dtsec.h>
+
+#include "../common/fman.h"
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+	int i;
+	struct memac_mdio_info dtsec_mdio_info;
+	struct memac_mdio_info tgec_mdio_info;
+	struct mii_dev *dev;
+	u32 srds_s1;
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) &
+			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	dtsec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the 1G MDIO bus */
+	fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+	tgec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+	/* Register the 10G MDIO bus */
+	fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+	/* Set the two on-board RGMII PHY address */
+	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
+
+	/* QSGMII on lane B, MAC 1/2/5/6 */
+	fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT1_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC2, QSGMII_PORT2_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT3_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT4_PHY_ADDR);
+
+	switch (srds_s1) {
+	case 0x1455:
+		break;
+	default:
+		printf("Invalid SerDes protocol 0x%x for LS1043ARDB\n",
+		       srds_s1);
+		break;
+	}
+
+	dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
+		fm_info_set_mdio(i, dev);
+
+	/* XFI on lane A, MAC 9 */
+	fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
+	dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+	fm_info_set_mdio(FM1_10GEC1, dev);
+
+	cpu_eth_init(bis);
+#endif
+
+	return pci_eth_init(bis);
+}
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index 076881c..fcefb17 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -16,6 +16,7 @@
 #include <scsi.h>
 #include <fsl_csu.h>
 #include <fsl_esdhc.h>
+#include <fm_eth.h>
 #include <fsl_ifc.h>
 #include "cpld.h"
 
@@ -111,6 +112,9 @@ int misc_init_r(void)
 
 int ft_board_setup(void *blob, bd_t *bd)
 {
+#ifdef CONFIG_SYS_DPAA_FMAN
+	fdt_fixup_fman_ethernet(blob);
+#endif
 	return 0;
 }
 
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index d052fcb..a3c9f99 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -37,3 +37,4 @@ obj-$(CONFIG_PPC_T4160) += t4240.o
 obj-$(CONFIG_PPC_T4080) += t4240.o
 obj-$(CONFIG_PPC_B4420) += b4860.o
 obj-$(CONFIG_PPC_B4860) += b4860.o
+obj-$(CONFIG_LS1043A)	+= ls1043.o
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index b3ff4c5..00a036c 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -1,13 +1,17 @@
 /*
- * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011-2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <errno.h>
 #include <common.h>
 #include <asm/io.h>
-#include <asm/fsl_serdes.h>
 #include <fsl_mdio.h>
+#ifdef CONFIG_FSL_LSCH2
+#include <asm/arch/fsl_serdes.h>
+#else
+#include <asm/fsl_serdes.h>
+#endif
 
 #include "fm.h"
 
@@ -153,7 +157,9 @@ void fm_disable_port(enum fm_port port)
 		return;
 
 	fm_info[i].enabled = 0;
+#ifndef CONFIG_SYS_FMAN_V3
 	fman_disable_port(port);
+#endif
 }
 
 void fm_enable_port(enum fm_port port)
diff --git a/drivers/net/fm/ls1043.c b/drivers/net/fm/ls1043.c
new file mode 100644
index 0000000..cf2cc95
--- /dev/null
+++ b/drivers/net/fm/ls1043.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <asm/arch/fsl_serdes.h>
+
+#define FSL_CHASSIS2_RCWSR13_EC1		0xe0000000 /* bits 416..418 */
+#define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII	0x00000000
+#define FSL_CHASSIS2_RCWSR13_EC1_GPIO		0x20000000
+#define FSL_CHASSIS2_RCWSR13_EC1_FTM		0xa0000000
+#define FSL_CHASSIS2_RCWSR13_EC2		0x1c000000 /* bits 419..421 */
+#define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII	0x00000000
+#define FSL_CHASSIS2_RCWSR13_EC2_GPIO		0x04000000
+#define FSL_CHASSIS2_RCWSR13_EC2_1588		0x08000000
+#define FSL_CHASSIS2_RCWSR13_EC2_FTM		0x14000000
+
+u32 port_to_devdisr[] = {
+	[FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1,
+	[FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2,
+	[FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3,
+	[FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4,
+	[FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5,
+	[FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6,
+	[FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9,
+	[FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10,
+	[FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1,
+	[FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2,
+	[FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3,
+	[FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4,
+};
+
+static int is_device_disabled(enum fm_port port)
+{
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 devdisr2 = in_be32(&gur->devdisr2);
+
+	return port_to_devdisr[port] & devdisr2;
+}
+
+void fman_disable_port(enum fm_port port)
+{
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+	setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
+}
+
+phy_interface_t fman_port_enet_if(enum fm_port port)
+{
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
+
+	if (is_device_disabled(port)) {
+		printf("%s:%d: port(%d) is disabled\n", __func__,
+		       __LINE__, port);
+		return PHY_INTERFACE_MODE_NONE;
+	}
+
+	if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
+		return PHY_INTERFACE_MODE_XGMII;
+
+	if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
+		return PHY_INTERFACE_MODE_NONE;
+
+	if (port == FM1_DTSEC3)
+		if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
+				FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) {
+			printf("%s:%d: port(FM1_DTSEC3) is OK\n",
+			       __func__, __LINE__);
+			return PHY_INTERFACE_MODE_RGMII;
+		}
+	if (port == FM1_DTSEC4)
+		if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
+				FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) {
+			printf("%s:%d: port(FM1_DTSEC4) is OK\n",
+			       __func__, __LINE__);
+			return PHY_INTERFACE_MODE_RGMII;
+		}
+
+	/* handle SGMII */
+	switch (port) {
+	case FM1_DTSEC1:
+	case FM1_DTSEC2:
+		if ((port == FM1_DTSEC2) &&
+		    is_serdes_configured(SGMII_2500_FM1_DTSEC2))
+			return PHY_INTERFACE_MODE_SGMII_2500;
+	case FM1_DTSEC5:
+	case FM1_DTSEC6:
+	case FM1_DTSEC9:
+		if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
+			return PHY_INTERFACE_MODE_SGMII;
+		else if ((port == FM1_DTSEC9) &&
+			 is_serdes_configured(SGMII_2500_FM1_DTSEC9))
+			return PHY_INTERFACE_MODE_SGMII_2500;
+		break;
+	default:
+		break;
+	}
+
+	/* handle QSGMII */
+	switch (port) {
+	case FM1_DTSEC1:
+	case FM1_DTSEC2:
+	case FM1_DTSEC5:
+	case FM1_DTSEC6:
+		/* only MAC 1,2,5,6 available for QSGMII */
+		if (is_serdes_configured(QSGMII_FM1_A))
+			return PHY_INTERFACE_MODE_QSGMII;
+		break;
+	default:
+		break;
+	}
+
+	return PHY_INTERFACE_MODE_NONE;
+}
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 5317976..3b0726c 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -115,6 +115,18 @@
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 
+/* FMan ucode */
+#define CONFIG_SYS_DPAA_FMAN
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_FM_MURAM_SIZE	0x60000
+
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+/* FMan fireware Pre-load address */
+#define CONFIG_SYS_FMAN_FW_ADDR		0x60300000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif
+
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
 #define CONFIG_ARCH_EARLY_INIT_R
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 5e6e09d..e612cee 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -228,4 +228,29 @@
 #define CONFIG_ENV_SIZE			0x20000
 #endif
 
+/* FMan */
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_MII
+#define CONFIG_PHYLIB
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_AQUANTIA
+
+#define RGMII_PHY1_ADDR			0x1
+#define RGMII_PHY2_ADDR			0x2
+
+#define QSGMII_PORT1_PHY_ADDR		0x4
+#define QSGMII_PORT2_PHY_ADDR		0x5
+#define QSGMII_PORT3_PHY_ADDR		0x6
+#define QSGMII_PORT4_PHY_ADDR		0x7
+
+#define FM1_10GEC1_PHY_ADDR		0x1
+
+#define CONFIG_ETHPRIME			"FM1 at DTSEC3"
+#endif
+
 #endif /* __LS1043ARDB_H__ */
-- 
2.1.0.27.g96db324

^ permalink raw reply related	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 14/16] armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardb
  2015-09-17  7:06 [U-Boot] [Patch v2 04/16] net/fm: bug fix when CONFIG_PHYLIB not defined Gong Qianyu
                   ` (8 preceding siblings ...)
  2015-09-17  7:06 ` [U-Boot] [Patch v2 13/16] armv8/ls1043a: Add Fman support Gong Qianyu
@ 2015-09-17  7:06 ` Gong Qianyu
  2015-09-17  7:06 ` [U-Boot] [Patch v2 15/16] armv8/ls1043ardb: Add sd boot support Gong Qianyu
  2015-09-17  7:06 ` [U-Boot] [Patch v2 16/16] armv8/ls1043ardb: Add cpld command to boot from sd Gong Qianyu
  11 siblings, 0 replies; 33+ messages in thread
From: Gong Qianyu @ 2015-09-17  7:06 UTC (permalink / raw)
  To: u-boot

From: Yangbo Lu <yangbo.lu@freescale.com>

This patch adds esdhc support for ls1043ardb.

Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
---
 arch/arm/cpu/armv8/fsl-lsch2/cpu.c   | 10 ++++++++++
 arch/arm/cpu/armv8/fsl-lsch2/fdt.c   |  6 ++++++
 arch/arm/cpu/armv8/fsl-lsch2/speed.c | 18 +++++++++++++++++-
 drivers/mmc/fsl_esdhc.c              | 13 +++++++------
 include/configs/ls1043a_common.h     | 11 +++++++++++
 include/fsl_esdhc.h                  |  2 +-
 6 files changed, 52 insertions(+), 8 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-lsch2/cpu.c b/arch/arm/cpu/armv8/fsl-lsch2/cpu.c
index 18886ea..e799c8b 100644
--- a/arch/arm/cpu/armv8/fsl-lsch2/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch2/cpu.c
@@ -12,6 +12,9 @@
 #include <asm/arch-fsl-lsch2/immap_lsch2.h>
 #include <asm/arch/fsl_serdes.h>
 #include <fm_eth.h>
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
 #include "speed.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -382,6 +385,13 @@ int print_cpuinfo(void)
 }
 #endif
 
+#ifdef CONFIG_FSL_ESDHC
+int cpu_mmc_init(bd_t *bis)
+{
+	return fsl_esdhc_mmc_init(bis);
+}
+#endif
+
 /*
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/fdt.c b/arch/arm/cpu/armv8/fsl-lsch2/fdt.c
index a646faa..f1ae1f1 100644
--- a/arch/arm/cpu/armv8/fsl-lsch2/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-lsch2/fdt.c
@@ -8,6 +8,9 @@
 #include <libfdt.h>
 #include <fdt_support.h>
 #include <phy.h>
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
 
 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 {
@@ -17,4 +20,7 @@ int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
+#if defined(CONFIG_FSL_ESDHC)
+	fdt_fixup_esdhc(blob, bd);
+#endif
 }
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/speed.c b/arch/arm/cpu/armv8/fsl-lsch2/speed.c
index 9ef630a..1c33284 100644
--- a/arch/arm/cpu/armv8/fsl-lsch2/speed.c
+++ b/arch/arm/cpu/armv8/fsl-lsch2/speed.c
@@ -25,7 +25,7 @@ void get_sys_info(struct sys_info *sys_info)
 	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
 	u32 ccr;
 #endif
-#ifdef CONFIG_SYS_DPAA_FMAN
+#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN)
 	u32 rcw_tmp;
 #endif
 	struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
@@ -105,6 +105,11 @@ void get_sys_info(struct sys_info *sys_info)
 
 #define HWA_CGA_M2_CLK_SEL	0x00000007
 #define HWA_CGA_M2_CLK_SHIFT	0
+#if defined(CONFIG_FSL_ESDHC)
+	rcw_tmp = in_be32(&gur->rcwsr[15]);
+	rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
+	sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
+#endif
 
 #if defined(CONFIG_FSL_IFC)
 	ccr = in_le32(&ifc_regs.gregs->ifc_ccr);
@@ -123,6 +128,10 @@ int get_clocks(void)
 	gd->bus_clk = sys_info.freq_systembus;
 	gd->mem_clk = sys_info.freq_ddrbus;
 
+#if defined(CONFIG_FSL_ESDHC)
+	gd->arch.sdhc_clk = sys_info.freq_sdhc;
+#endif
+
 	if (gd->cpu_clk != 0)
 		return 0;
 	else
@@ -139,6 +148,11 @@ ulong get_ddr_freq(ulong dummy)
 	return gd->mem_clk;
 }
 
+int get_sdhc_freq(ulong dummy)
+{
+	return gd->arch.sdhc_clk;
+}
+
 int get_serial_clock(void)
 {
 	return gd->bus_clk;
@@ -149,6 +163,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 	switch (clk) {
 	case MXC_I2C_CLK:
 		return get_bus_freq(0);
+	case MXC_ESDHC_CLK:
+		return get_sdhc_freq(0);
 	case MXC_DSPI_CLK:
 		return get_bus_freq(0);
 	case MXC_UART_CLK:
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 0b37002..0a22874 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -106,7 +106,8 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
 		xfertyp |= XFERTYP_RSPTYP_48;
 
 #if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \
-	defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A)
+	defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A) || \
+	defined(CONFIG_LS1043A)
 	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 		xfertyp |= XFERTYP_CMDTYP_ABORT;
 #endif
@@ -184,7 +185,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 	int timeout;
 	struct fsl_esdhc_cfg *cfg = mmc->priv;
 	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
-#ifdef CONFIG_LS2085A
+#if defined(CONFIG_LS2085A) || defined(CONFIG_LS1043A)
 	dma_addr_t addr;
 #endif
 	uint wml_value;
@@ -197,7 +198,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 
 		esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#ifdef CONFIG_LS2085A
+#if defined(CONFIG_LS2085A) || defined(CONFIG_LS1043A)
 		addr = virt_to_phys((void *)(data->dest));
 		if (upper_32_bits(addr))
 			printf("Error found for upper 32 bits\n");
@@ -223,7 +224,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 		esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
 					wml_value << 16);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#ifdef CONFIG_LS2085A
+#if defined(CONFIG_LS2085A) || defined(CONFIG_LS1043A)
 		addr = virt_to_phys((void *)(data->src));
 		if (upper_32_bits(addr))
 			printf("Error found for upper 32 bits\n");
@@ -277,7 +278,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 static void check_and_invalidate_dcache_range
 	(struct mmc_cmd *cmd,
 	 struct mmc_data *data) {
-#ifdef CONFIG_LS2085A
+#if defined(CONFIG_LS2085A) || defined(CONFIG_LS1043A)
 	unsigned start = 0;
 #else
 	unsigned start = (unsigned)data->dest ;
@@ -285,7 +286,7 @@ static void check_and_invalidate_dcache_range
 	unsigned size = roundup(ARCH_DMA_MINALIGN,
 				data->blocks*data->blocksize);
 	unsigned end = start+size ;
-#ifdef CONFIG_LS2085A
+#if defined(CONFIG_LS2085A) || defined(CONFIG_LS1043A)
 	dma_addr_t addr;
 
 	addr = virt_to_phys((void *)(data->dest));
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 3b0726c..c62d8fa 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -115,6 +115,17 @@
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 
+/*  MMC  */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
 /* FMan ucode */
 #define CONFIG_SYS_DPAA_FMAN
 #ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 0d00b7d..b6572e7 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -166,7 +166,7 @@
 #define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
 
 struct fsl_esdhc_cfg {
-#ifdef CONFIG_LS2085A
+#if defined(CONFIG_LS2085A) || defined(CONFIG_LS1043A)
 	u64	esdhc_base;
 #else
 	u32	esdhc_base;
-- 
2.1.0.27.g96db324

^ permalink raw reply related	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 15/16] armv8/ls1043ardb: Add sd boot support
  2015-09-17  7:06 [U-Boot] [Patch v2 04/16] net/fm: bug fix when CONFIG_PHYLIB not defined Gong Qianyu
                   ` (9 preceding siblings ...)
  2015-09-17  7:06 ` [U-Boot] [Patch v2 14/16] armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardb Gong Qianyu
@ 2015-09-17  7:06 ` Gong Qianyu
  2015-09-17  7:06 ` [U-Boot] [Patch v2 16/16] armv8/ls1043ardb: Add cpld command to boot from sd Gong Qianyu
  11 siblings, 0 replies; 33+ messages in thread
From: Gong Qianyu @ 2015-09-17  7:06 UTC (permalink / raw)
  To: u-boot

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
---
 board/freescale/ls1043ardb/ls1043ardb.c          |  8 +++++++
 board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg |  7 ++++++
 configs/ls1043ardb_sdcard_defconfig              |  4 ++++
 include/configs/ls1043a_common.h                 | 30 ++++++++++++++++++++++++
 include/configs/ls1043ardb.h                     | 13 ++++++++--
 5 files changed, 60 insertions(+), 2 deletions(-)

diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index fcefb17..edc6bc9 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -12,12 +12,14 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
 #include <hwconfig.h>
+#include <mmc.h>
 #include <ahci.h>
 #include <scsi.h>
 #include <fsl_csu.h>
 #include <fsl_esdhc.h>
 #include <fm_eth.h>
 #include <fsl_ifc.h>
+#include <spl.h>
 #include "cpld.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -25,12 +27,17 @@ DECLARE_GLOBAL_DATA_PTR;
 int checkboard(void)
 {
 	static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
+#ifndef CONFIG_SD_BOOT
 	u8 cfg_rcw_src1, cfg_rcw_src2;
 	u32 cfg_rcw_src;
+#endif
 	u32 sd1refclk_sel;
 
 	printf("Board: LS1043ARDB, boot from ");
 
+#ifdef CONFIG_SD_BOOT
+	puts("SD\n");
+#else
 	cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
 	cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
 	cpld_rev_bit(&cfg_rcw_src1);
@@ -43,6 +50,7 @@ int checkboard(void)
 		puts("NAND\n");
 	else
 		printf("Invalid setting of SW4\n");
+#endif
 
 	printf("CPLD:  V%x.%x\nPCBA:  V%x.0\n", CPLD_READ(cpld_ver),
 	       CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
new file mode 100644
index 0000000..28cd958
--- /dev/null
+++ b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+0810000f 0c000000 00000000 00000000
+14550002 80004012 60040000 61002000
+00000000 00000000 00000000 00038800
+00000000 00001100 00000096 00000001
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
new file mode 100644
index 0000000..5fe0470
--- /dev/null
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043ARDB=y
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index c62d8fa..3485bed 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -60,6 +60,36 @@
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
+/* SD boot SPL */
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR		0xf0
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS		0x500
+
+#define CONFIG_SPL_TEXT_BASE		0x10000000
+#define CONFIG_SPL_MAX_SIZE		0x1d000
+#define CONFIG_SPL_STACK		0x1001e000
+#define CONFIG_SPL_PAD_TO		0x1d000
+
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
+					CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+#define CONFIG_SPL_BSS_START_ADDR	0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_MONITOR_LEN		0xa0000
+#endif
+
 /* NAND SPL */
 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_SPL_PBL_PAD
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index e612cee..4565500 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -12,7 +12,7 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
-#if defined(CONFIG_NAND_BOOT)
+#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
 #define CONFIG_SYS_TEXT_BASE		0x82000000
 #else
 #define CONFIG_SYS_TEXT_BASE		0x60100000
@@ -45,6 +45,10 @@
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
 #endif
 
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
+#endif
+
 /*
  * NOR Flash Definitions
  */
@@ -217,7 +221,12 @@
  */
 #define CONFIG_ENV_OVERWRITE
 
-#if defined(CONFIG_NAND_BOOT)
+#if defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET		(1024 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			0x2000
+#elif defined(CONFIG_NAND_BOOT)
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
-- 
2.1.0.27.g96db324

^ permalink raw reply related	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 16/16] armv8/ls1043ardb: Add cpld command to boot from sd
  2015-09-17  7:06 [U-Boot] [Patch v2 04/16] net/fm: bug fix when CONFIG_PHYLIB not defined Gong Qianyu
                   ` (10 preceding siblings ...)
  2015-09-17  7:06 ` [U-Boot] [Patch v2 15/16] armv8/ls1043ardb: Add sd boot support Gong Qianyu
@ 2015-09-17  7:06 ` Gong Qianyu
  2015-09-21 17:27   ` York Sun
  11 siblings, 1 reply; 33+ messages in thread
From: Gong Qianyu @ 2015-09-17  7:06 UTC (permalink / raw)
  To: u-boot

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
---
 board/freescale/ls1043ardb/cpld.c | 17 +++++++++++++++++
 board/freescale/ls1043ardb/cpld.h |  1 +
 2 files changed, 18 insertions(+)

diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c
index 5acb97d..faa0de8 100644
--- a/board/freescale/ls1043ardb/cpld.c
+++ b/board/freescale/ls1043ardb/cpld.c
@@ -60,6 +60,20 @@ void cpld_set_nand(void)
 	CPLD_WRITE(system_rst, 1);
 }
 
+void cpld_set_sd(void)
+{
+	u16 reg = CPLD_CFG_RCW_SRC_SD;
+	u8 reg5 = (u8)(reg >> 1);
+	u8 reg6 = (u8)(reg & 1);
+	cpld_rev_bit(&reg5);
+
+	CPLD_WRITE(soft_mux_on, 1);
+
+	CPLD_WRITE(cfg_rcw_src1, reg5);
+	CPLD_WRITE(cfg_rcw_src2, reg6);
+
+	CPLD_WRITE(system_rst, 1);
+}
 #ifdef DEBUG
 static void cpld_dump_regs(void)
 {
@@ -108,6 +122,8 @@ int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			cpld_set_altbank();
 		else if (strcmp(argv[2], "nand") == 0)
 			cpld_set_nand();
+		else if (strcmp(argv[2], "sd") == 0)
+			cpld_set_sd();
 		else
 			cpld_set_defbank();
 #ifdef DEBUG
@@ -127,6 +143,7 @@ U_BOOT_CMD(
 	"reset: reset to default bank\n"
 	"cpld reset altbank: reset to alternate bank\n"
 	"cpld reset nand: reset to boot from NAND flash\n"
+	"cpld reset sd: reset to boot from SD card\n"
 #ifdef DEBUG
 	"cpld dump - display the CPLD registers\n"
 #endif
diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h
index 5f43a8a..bd59c0e 100644
--- a/board/freescale/ls1043ardb/cpld.h
+++ b/board/freescale/ls1043ardb/cpld.h
@@ -41,4 +41,5 @@ void cpld_rev_bit(unsigned char *value);
 #define CPLD_BANK_SEL_MASK	0x07
 #define CPLD_BANK_SEL_ALTBANK	0x04
 #define CPLD_CFG_RCW_SRC_NAND	0x106
+#define CPLD_CFG_RCW_SRC_SD	0x040
 #endif
-- 
2.1.0.27.g96db324

^ permalink raw reply related	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 07/16] net/fm: fix MDIO controller base on FMAN2
  2015-09-17  7:06 ` [U-Boot] [Patch v2 07/16] net/fm: fix MDIO controller base on FMAN2 Gong Qianyu
@ 2015-09-17 18:04   ` Scott Wood
  2015-09-18  3:49     ` Shaohui Xie
  0 siblings, 1 reply; 33+ messages in thread
From: Scott Wood @ 2015-09-17 18:04 UTC (permalink / raw)
  To: u-boot

On Thu, 2015-09-17 at 15:06 +0800, Gong Qianyu wrote:
> From: Shaohui Xie <Shaohui.Xie@freescale.com>
> 
> MDIO controller base on FMAN2 was defined as CONFIG_SYS_FSL_FM2_ADDR
> plus offset, but CONFIG_SYS_FSL_FM2_ADDR only defined when there are two
> FMANs, so we should only define MDIO controller base on FMAN2 when there
> is FMAN2.
> 
> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
> ---
>  include/fm_eth.h | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/include/fm_eth.h b/include/fm_eth.h
> index 3e1b9f4..d43f801 100644
> --- a/include/fm_eth.h
> +++ b/include/fm_eth.h
> @@ -45,8 +45,10 @@ enum fm_eth_type {
>  #ifdef CONFIG_SYS_FMAN_V3
>  #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR       (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
>  #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR        (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
> +#if (CONFIG_SYS_NUM_FMAN == 2)
>  #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR       (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)
>  #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR        (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000)
> +#endif
>  #else
>  #define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR      (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120)
>  #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR        (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000)
> @@ -89,6 +91,7 @@ enum fm_eth_type {
>                                offsetof(struct ccsr_fman, memac[n-1]),\
>  }
>  #else
> +#if (CONFIG_SYS_NUM_FMAN == 2)
> #define FM_TGEC_INFO_INITIALIZER(idx, n) \
>  {                                                                    \
>       FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR)     \
> @@ -101,6 +104,20 @@ enum fm_eth_type {
>       .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
>                               offsetof(struct ccsr_fman, memac[n-1+8]),\
>  }
> +#else
> +#define FM_TGEC_INFO_INITIALIZER(idx, n) \
> +{                                                                    \
> +     FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)     \
> +     .index          = idx,                                          \
> +     .num            = n - 1,                                        \
> +     .type           = FM_ETH_10G_E,                                 \
> +     .port           = FM##idx##_10GEC##n,                           \
> +     .rx_port_id     = RX_PORT_10G_BASE + n - 1,                     \
> +     .tx_port_id     = TX_PORT_10G_BASE + n - 1,                     \
> +     .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
> +                             offsetof(struct ccsr_fman, memac[n-1+8]),\
> +}
> +#endif
>  #endif

doc/README.fsl-dpaa says that CONFIG_FSL_FM_10GEC_REGULAR_NOTATION is for 
newer SoCs.  Presumably this patch is for ls1043a -- is that not considered a 
newer SoC?  Or does the README need to be fixed?

-Scott

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 05/16] net: Move some header files to include/
  2015-09-17  7:06 ` [U-Boot] [Patch v2 05/16] net: Move some header files to include/ Gong Qianyu
@ 2015-09-17 18:06   ` Scott Wood
  0 siblings, 0 replies; 33+ messages in thread
From: Scott Wood @ 2015-09-17 18:06 UTC (permalink / raw)
  To: u-boot

On Thu, 2015-09-17 at 15:06 +0800, Gong Qianyu wrote:
> From: Shaohui Xie <Shaohui.Xie@freescale.com>
> 
> The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM
> and PPC, move it out of ppc to include/, and change the path in
> drivers accordingly.
> 
> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>

Pass -M -C to git format-patch.

-Scott

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 08/16] net/fm: fix compile warnings for 64-bit platform
  2015-09-17  7:06 ` [U-Boot] [Patch v2 08/16] net/fm: fix compile warnings for 64-bit platform Gong Qianyu
@ 2015-09-17 18:13   ` Scott Wood
  2015-09-25  2:22     ` Hou Zhiqiang
  0 siblings, 1 reply; 33+ messages in thread
From: Scott Wood @ 2015-09-17 18:13 UTC (permalink / raw)
  To: u-boot

On Thu, 2015-09-17 at 15:06 +0800, Gong Qianyu wrote:
> This patch fixes such compile warnings:
> 
> drivers/net/fm/eth.c: In function 'fm_eth_recv':
> drivers/net/fm/eth.c:549:11: warning: cast to pointer from integer of
> different size [-Wint-to-pointer-cast]
>       data = (u8 *)in_be32(&rxbd->buf_ptr_lo);
> drivers/net/fm/fm.c: In function 'fm_muram_alloc':
> drivers/net/fm/fm.c:52:9: warning: cast to pointer from integer of
> different size [-Wint-to-pointer-cast]
>       memset((void *)ret, 0, size);
> drivers/net/fm/fm.c: In function 'fm_init_muram':
> drivers/net/fm/fm.c:59:13: warning: cast from pointer to integer of
> different size [-Wpointer-to-int-cast]
>       u32 base = (u32)reg;
> 
> Just make the cast explicit for them.
> 
> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
> ---
>  drivers/net/fm/eth.c | 31 ++++++++++++++++---------------
>  drivers/net/fm/fm.c  |  4 ++--
>  2 files changed, 18 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
> index 12eb9b8..6ef0afb 100644
> --- a/drivers/net/fm/eth.c
> +++ b/drivers/net/fm/eth.c
> @@ -120,12 +120,12 @@ static int tgec_is_fibre(struct eth_device *dev)
>  
>  static u16 muram_readw(u16 *addr)
>  {
> -     u32 base = (u32)addr & ~0x3;
> +     ulong base = (ulong)addr & ~0x3;

This will still truncate the address at 32 bits.  It needs to be ~0x3UL.


>       u32 val32 = in_be32((u32 *)base);
>       int byte_pos;
>       u16 ret;
>  
> -     byte_pos = (u32)addr & 0x3;
> +     byte_pos = (ulong)addr & 0x3;
>       if (byte_pos)
>               ret = (u16)(val32 & 0x0000ffff);
>       else
> @@ -136,12 +136,12 @@ static u16 muram_readw(u16 *addr)
>  
>  static void muram_writew(u16 *addr, u16 val)
>  {
> -     u32 base = (u32)addr & ~0x3;
> +     ulong base = (ulong)addr & ~0x3;
>       u32 org32 = in_be32((u32 *)base);
>       u32 val32;
>       int byte_pos;
>  
> -     byte_pos = (u32)addr & 0x3;
> +     byte_pos = (ulong)addr & 0x3;
>       if (byte_pos)
>               val32 = (org32 & 0xffff0000) | val;
>       else
> @@ -217,12 +217,12 @@ static int fm_eth_rx_port_parameter_init(struct 
> fm_eth *fm_eth)
>       int i;
>  
>       /* alloc global parameter ram at MURAM */
> -     pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
> -             FM_PRAM_SIZE, FM_PRAM_ALIGN);
> +     pram = (struct fm_port_global_pram *)(ulong)fm_muram_alloc(
> +                     fm_eth->fm_index, FM_PRAM_SIZE, FM_PRAM_ALIGN);

Make fm_muram_alloc() return a pointer instead.  If muram were >= 4 GiB the 
above would fail.

>       fm_eth->rx_pram = pram;
>  
>       /* parameter page offset to MURAM */
> -     pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
> +     pram_page_offset = (u32)(ulong)pram - fm_muram_base(fm_eth->fm_index);

Get rid of the u32 cast -- again, if the muram base were above >= 4 GiB this 
would fail because you're dropping the high bits before the subtraction 
rather than after.

>  
>       /* enable global mode- snooping data buffers and BDs */
>       out_be32(&pram->mode, PRAM_MODE_GLOBAL);
> @@ -258,7 +258,8 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth 
> *fm_eth)
>               muram_writew(&rxbd->status, RxBD_EMPTY);
>               muram_writew(&rxbd->len, 0);
>               muram_writew(&rxbd->buf_ptr_hi, 0);
> -             out_be32(&rxbd->buf_ptr_lo, (u32)rx_buf_pool + i * MAX_RXBUF_LEN);
> +             out_be32(&rxbd->buf_ptr_lo, (u32)(ulong)rx_buf_pool +
> +                                                     i * MAX_RXBUF_LEN);
>               rxbd++;

Use virt_to_phys() and lower_32_bits().  Is there a "hi" register to handle 
the upper 32 bits?

Likewise elsewhere.  Don't just apply the minimum bandage to get rid of the 
warning.  Make the code actually be 64-bit clean.

-Scott

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 11/16] armv8/ls1043ardb: Add nand boot support
  2015-09-17  7:06 ` [U-Boot] [Patch v2 11/16] armv8/ls1043ardb: Add nand boot support Gong Qianyu
@ 2015-09-17 20:16   ` Scott Wood
  2015-09-18  3:36     ` Gong Q.Y.
  0 siblings, 1 reply; 33+ messages in thread
From: Scott Wood @ 2015-09-17 20:16 UTC (permalink / raw)
  To: u-boot

On Thu, 2015-09-17 at 15:06 +0800, Gong Qianyu wrote:
> 

>  
> +/* NAND SPL */
> +#ifdef CONFIG_NAND_BOOT
> +#define CONFIG_SPL_PBL_PAD
> +#define CONFIG_SPL_FRAMEWORK
> +#define CONFIG_SPL_LDSCRIPT          "arch/arm/cpu/armv8/u-boot-spl.lds"
> +#define CONFIG_SPL_TARGET            "u-boot-with-spl.bin"
> +#define CONFIG_SPL_LIBCOMMON_SUPPORT
> +#define CONFIG_SPL_LIBGENERIC_SUPPORT
> +#define CONFIG_SPL_ENV_SUPPORT
> +#define CONFIG_SPL_WATCHDOG_SUPPORT
> +#define CONFIG_SPL_I2C_SUPPORT
> +#define CONFIG_SPL_SERIAL_SUPPORT
> +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
> +#define CONFIG_SPL_NAND_SUPPORT
> +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
> +#define CONFIG_SPL_TEXT_BASE         0x10000000
> +#define CONFIG_SPL_MAX_SIZE          0x1a000
> +#define CONFIG_SPL_STACK             0x1001d000
> +#define CONFIG_SPL_PAD_TO            0x1c000
> +#define CONFIG_SYS_NAND_U_BOOT_OFFS  CONFIG_SPL_PAD_TO
> +#define CONFIG_SYS_NAND_U_BOOT_SIZE  (640 << 10)

You made the U-Boot size be block aligned (assuming 128k block size, which 
the SoC common file should not do), but its offset is not.

-Scott

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 11/16] armv8/ls1043ardb: Add nand boot support
  2015-09-17 20:16   ` Scott Wood
@ 2015-09-18  3:36     ` Gong Q.Y.
  2015-09-18  5:14       ` Scott Wood
  0 siblings, 1 reply; 33+ messages in thread
From: Gong Q.Y. @ 2015-09-18  3:36 UTC (permalink / raw)
  To: u-boot


> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Friday, September 18, 2015 4:16 AM
> To: Gong Qianyu-B52263
> Cc: u-boot at lists.denx.de; Hu Mingkai-B21284; Sun York-R58495; Hou
> Zhiqiang-B48286; Song Wenbin-B53747; Xie Shaohui-B21989; Wood Scott-
> B07421
> Subject: Re: [Patch v2 11/16] armv8/ls1043ardb: Add nand boot support
> 
> On Thu, 2015-09-17 at 15:06 +0800, Gong Qianyu wrote:
> >
> 
> >
> > +/* NAND SPL */
> > +#ifdef CONFIG_NAND_BOOT
> > +#define CONFIG_SPL_PBL_PAD
> > +#define CONFIG_SPL_FRAMEWORK
> > +#define CONFIG_SPL_LDSCRIPT          "arch/arm/cpu/armv8/u-boot-
> spl.lds"
> > +#define CONFIG_SPL_TARGET            "u-boot-with-spl.bin"
> > +#define CONFIG_SPL_LIBCOMMON_SUPPORT
> > +#define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_ENV_SUPPORT
> > +#define CONFIG_SPL_WATCHDOG_SUPPORT #define CONFIG_SPL_I2C_SUPPORT
> > +#define CONFIG_SPL_SERIAL_SUPPORT #define
> > +CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
> > +#define CONFIG_SPL_NAND_SUPPORT
> > +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
> > +#define CONFIG_SPL_TEXT_BASE         0x10000000
> > +#define CONFIG_SPL_MAX_SIZE          0x1a000
> > +#define CONFIG_SPL_STACK             0x1001d000
> > +#define CONFIG_SPL_PAD_TO            0x1c000
> > +#define CONFIG_SYS_NAND_U_BOOT_OFFS  CONFIG_SPL_PAD_TO #define
> > +CONFIG_SYS_NAND_U_BOOT_SIZE  (640 << 10)
> 
> You made the U-Boot size be block aligned (assuming 128k block size,
> which the SoC common file should not do), but its offset is not.
> 
> -Scott

Eh, yes. The CONFIG_SPL_PAD_TO should be block aligned and put to board specific file assuming different NAND chips.
That reminds me. SPL and U-Boot size should be block aligned, so it is with the env size. Right?

Regards,
Qianyu

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 07/16] net/fm: fix MDIO controller base on FMAN2
  2015-09-17 18:04   ` Scott Wood
@ 2015-09-18  3:49     ` Shaohui Xie
  2015-09-18  5:13       ` Scott Wood
  0 siblings, 1 reply; 33+ messages in thread
From: Shaohui Xie @ 2015-09-18  3:49 UTC (permalink / raw)
  To: u-boot

> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Friday, September 18, 2015 2:05 AM
> To: Gong Qianyu-B52263
> Cc: u-boot at lists.denx.de; Hu Mingkai-B21284; Sun York-R58495; Hou
> Zhiqiang-B48286; Song Wenbin-B53747; Xie Shaohui-B21989; Wood Scott-
> B07421
> Subject: Re: [Patch v2 07/16] net/fm: fix MDIO controller base on FMAN2
> 
> On Thu, 2015-09-17 at 15:06 +0800, Gong Qianyu wrote:
> > From: Shaohui Xie <Shaohui.Xie@freescale.com>
> >
> > MDIO controller base on FMAN2 was defined as CONFIG_SYS_FSL_FM2_ADDR
> > plus offset, but CONFIG_SYS_FSL_FM2_ADDR only defined when there are
> > two FMANs, so we should only define MDIO controller base on FMAN2 when
> > there is FMAN2.
> >
> > Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
> > Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
> > Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
> > ---
> >  include/fm_eth.h | 17 +++++++++++++++++
> >  1 file changed, 17 insertions(+)
> >
> > diff --git a/include/fm_eth.h b/include/fm_eth.h index
> > 3e1b9f4..d43f801 100644
> > --- a/include/fm_eth.h
> > +++ b/include/fm_eth.h
> > @@ -45,8 +45,10 @@ enum fm_eth_type {
> >  #ifdef CONFIG_SYS_FMAN_V3
> >  #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR       (CONFIG_SYS_FSL_FM1_ADDR
> + 0xfc000)
> >  #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR        (CONFIG_SYS_FSL_FM1_ADDR
> + 0xfd000)
> > +#if (CONFIG_SYS_NUM_FMAN == 2)
> >  #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR       (CONFIG_SYS_FSL_FM2_ADDR
> + 0xfc000)
> >  #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR        (CONFIG_SYS_FSL_FM2_ADDR
> + 0xfd000)
> > +#endif
> >  #else
> >  #define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR      (CONFIG_SYS_FSL_FM1_ADDR
> + 0xe1120)
> >  #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR        (CONFIG_SYS_FSL_FM1_ADDR
> + 0xf1000)
> > @@ -89,6 +91,7 @@ enum fm_eth_type {
> >                                offsetof(struct ccsr_fman,
> > memac[n-1]),\  }  #else
> > +#if (CONFIG_SYS_NUM_FMAN == 2)
> > #define FM_TGEC_INFO_INITIALIZER(idx, n) \
> >  {                                                                    \
> >       FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR)     \
> > @@ -101,6 +104,20 @@ enum fm_eth_type {
> >       .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
> >                               offsetof(struct ccsr_fman,
> > memac[n-1+8]),\  }
> > +#else
> > +#define FM_TGEC_INFO_INITIALIZER(idx, n) \
> > +{                                                                    \
> > +     FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)     \
> > +     .index          = idx,                                          \
> > +     .num            = n - 1,                                        \
> > +     .type           = FM_ETH_10G_E,                                 \
> > +     .port           = FM##idx##_10GEC##n,                           \
> > +     .rx_port_id     = RX_PORT_10G_BASE + n - 1,                     \
> > +     .tx_port_id     = TX_PORT_10G_BASE + n - 1,                     \
> > +     .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
> > +                             offsetof(struct ccsr_fman,
> > +memac[n-1+8]),\ } #endif
> >  #endif
> 
> doc/README.fsl-dpaa says that CONFIG_FSL_FM_10GEC_REGULAR_NOTATION is for
> newer SoCs.  Presumably this patch is for ls1043a -- is that not
> considered a newer SoC?  Or does the README need to be fixed?
[S.H] Yes, this is for LS1043A. LS1043A has one FMAN same as T2080. 
A new SoC but has an old DPAA.

The issue this patch intends to fix is there is only one FMAN on LS1043A,
So CONFIG_SYS_FSL_FM2_ADDR is not defined on LS1043A, the define of MDIO controller base
On FMAN2 uses CONFIG_SYS_FSL_FM2_ADDR caused error on LS1043A.

Thanks!
Shaohui

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 07/16] net/fm: fix MDIO controller base on FMAN2
  2015-09-18  3:49     ` Shaohui Xie
@ 2015-09-18  5:13       ` Scott Wood
  2015-09-25 10:51         ` Hu Vincent
  0 siblings, 1 reply; 33+ messages in thread
From: Scott Wood @ 2015-09-18  5:13 UTC (permalink / raw)
  To: u-boot

On Thu, 2015-09-17 at 22:49 -0500, Xie Shaohui-B21989 wrote:
> > -----Original Message-----
> > From: Wood Scott-B07421
> > Sent: Friday, September 18, 2015 2:05 AM
> > To: Gong Qianyu-B52263
> > Cc: u-boot at lists.denx.de; Hu Mingkai-B21284; Sun York-R58495; Hou
> > Zhiqiang-B48286; Song Wenbin-B53747; Xie Shaohui-B21989; Wood Scott-
> > B07421
> > Subject: Re: [Patch v2 07/16] net/fm: fix MDIO controller base on FMAN2
> > 
> > On Thu, 2015-09-17 at 15:06 +0800, Gong Qianyu wrote:
> > > From: Shaohui Xie <Shaohui.Xie@freescale.com>
> > > 
> > > MDIO controller base on FMAN2 was defined as CONFIG_SYS_FSL_FM2_ADDR
> > > plus offset, but CONFIG_SYS_FSL_FM2_ADDR only defined when there are
> > > two FMANs, so we should only define MDIO controller base on FMAN2 when
> > > there is FMAN2.
> > > 
> > > Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
> > > Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
> > > Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
> > > ---
> > >  include/fm_eth.h | 17 +++++++++++++++++
> > >  1 file changed, 17 insertions(+)
> > > 
> > > diff --git a/include/fm_eth.h b/include/fm_eth.h index
> > > 3e1b9f4..d43f801 100644
> > > --- a/include/fm_eth.h
> > > +++ b/include/fm_eth.h
> > > @@ -45,8 +45,10 @@ enum fm_eth_type {
> > >  #ifdef CONFIG_SYS_FMAN_V3
> > >  #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR       (CONFIG_SYS_FSL_FM1_ADDR
> > + 0xfc000)
> > >  #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR        (CONFIG_SYS_FSL_FM1_ADDR
> > + 0xfd000)
> > > +#if (CONFIG_SYS_NUM_FMAN == 2)
> > >  #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR       (CONFIG_SYS_FSL_FM2_ADDR
> > + 0xfc000)
> > >  #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR        (CONFIG_SYS_FSL_FM2_ADDR
> > + 0xfd000)
> > > +#endif
> > >  #else
> > >  #define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR      (CONFIG_SYS_FSL_FM1_ADDR
> > + 0xe1120)
> > >  #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR        (CONFIG_SYS_FSL_FM1_ADDR
> > + 0xf1000)
> > > @@ -89,6 +91,7 @@ enum fm_eth_type {
> > >                                offsetof(struct ccsr_fman,
> > > memac[n-1]),\  }  #else
> > > +#if (CONFIG_SYS_NUM_FMAN == 2)
> > > #define FM_TGEC_INFO_INITIALIZER(idx, n) \
> > >  {                                                                    \
> > >       FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR)     \
> > > @@ -101,6 +104,20 @@ enum fm_eth_type {
> > >       .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
> > >                               offsetof(struct ccsr_fman,
> > > memac[n-1+8]),\  }
> > > +#else
> > > +#define FM_TGEC_INFO_INITIALIZER(idx, n) \
> > > +{                                                                    \
> > > +     FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)     \
> > > +     .index          = idx,                                          \
> > > +     .num            = n - 1,                                        \
> > > +     .type           = FM_ETH_10G_E,                                 \
> > > +     .port           = FM##idx##_10GEC##n,                           \
> > > +     .rx_port_id     = RX_PORT_10G_BASE + n - 1,                     \
> > > +     .tx_port_id     = TX_PORT_10G_BASE + n - 1,                     \
> > > +     .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
> > > +                             offsetof(struct ccsr_fman,
> > > +memac[n-1+8]),\ } #endif
> > >  #endif
> > 
> > doc/README.fsl-dpaa says that CONFIG_FSL_FM_10GEC_REGULAR_NOTATION is for
> > newer SoCs.  Presumably this patch is for ls1043a -- is that not
> > considered a newer SoC?  Or does the README need to be fixed?
> [S.H] Yes, this is for LS1043A. LS1043A has one FMAN same as T2080. 
> A new SoC but has an old DPAA.

So maybe the README should be changed to more accurately talk about FMan 
versions?

-Scott

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 11/16] armv8/ls1043ardb: Add nand boot support
  2015-09-18  3:36     ` Gong Q.Y.
@ 2015-09-18  5:14       ` Scott Wood
  0 siblings, 0 replies; 33+ messages in thread
From: Scott Wood @ 2015-09-18  5:14 UTC (permalink / raw)
  To: u-boot

On Thu, 2015-09-17 at 22:36 -0500, Gong Qianyu-B52263 wrote:
> > -----Original Message-----
> > From: Wood Scott-B07421
> > Sent: Friday, September 18, 2015 4:16 AM
> > To: Gong Qianyu-B52263
> > Cc: u-boot at lists.denx.de; Hu Mingkai-B21284; Sun York-R58495; Hou
> > Zhiqiang-B48286; Song Wenbin-B53747; Xie Shaohui-B21989; Wood Scott-
> > B07421
> > Subject: Re: [Patch v2 11/16] armv8/ls1043ardb: Add nand boot support
> > 
> > On Thu, 2015-09-17 at 15:06 +0800, Gong Qianyu wrote:
> > > 
> > 
> > > 
> > > +/* NAND SPL */
> > > +#ifdef CONFIG_NAND_BOOT
> > > +#define CONFIG_SPL_PBL_PAD
> > > +#define CONFIG_SPL_FRAMEWORK
> > > +#define CONFIG_SPL_LDSCRIPT          "arch/arm/cpu/armv8/u-boot-
> > spl.lds"
> > > +#define CONFIG_SPL_TARGET            "u-boot-with-spl.bin"
> > > +#define CONFIG_SPL_LIBCOMMON_SUPPORT
> > > +#define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_ENV_SUPPORT
> > > +#define CONFIG_SPL_WATCHDOG_SUPPORT #define CONFIG_SPL_I2C_SUPPORT
> > > +#define CONFIG_SPL_SERIAL_SUPPORT #define
> > > +CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
> > > +#define CONFIG_SPL_NAND_SUPPORT
> > > +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
> > > +#define CONFIG_SPL_TEXT_BASE         0x10000000
> > > +#define CONFIG_SPL_MAX_SIZE          0x1a000
> > > +#define CONFIG_SPL_STACK             0x1001d000
> > > +#define CONFIG_SPL_PAD_TO            0x1c000
> > > +#define CONFIG_SYS_NAND_U_BOOT_OFFS  CONFIG_SPL_PAD_TO #define
> > > +CONFIG_SYS_NAND_U_BOOT_SIZE  (640 << 10)
> > 
> > You made the U-Boot size be block aligned (assuming 128k block size,
> > which the SoC common file should not do), but its offset is not.
> > 
> > -Scott
> 
> Eh, yes. The CONFIG_SPL_PAD_TO should be block aligned and put to board 
> specific file assuming different NAND chips.

Yes.

> That reminds me. SPL and U-Boot size should be block aligned, so it is with 
> the env size. Right?

The environment should have a full block reserved to it, but the actual 
environment size does not need to take up the full block.  Typically U-Boot 
environments are smaller than a flash block, probably to reduce the amount of 
CRC that needs to be calculated.

-Scott

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 09/16] ARMv8/FSL_LSCH2: Add FSL_LSCH2 SoC
  2015-09-17  7:06 ` [U-Boot] [Patch v2 09/16] ARMv8/FSL_LSCH2: Add FSL_LSCH2 SoC Gong Qianyu
@ 2015-09-21 17:27   ` York Sun
  2015-09-25 12:28     ` Hu Vincent
  0 siblings, 1 reply; 33+ messages in thread
From: York Sun @ 2015-09-21 17:27 UTC (permalink / raw)
  To: u-boot



On 09/17/2015 12:06 AM, Gong Qianyu wrote:
> From: Mingkai Hu <Mingkai.Hu@freescale.com>
> 
> Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
> ARMv8 cores and 2rd generation of Chassis.
> 
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
> ---
> V2:
> remove FSL_LS102xA_DEVDISR3_PCIE from immap_lsch2.h
> 
>  arch/arm/cpu/armv8/Makefile                       |   1 +
>  arch/arm/cpu/armv8/fsl-lsch2/Makefile             |  12 +
>  arch/arm/cpu/armv8/fsl-lsch2/README               |  10 +
>  arch/arm/cpu/armv8/fsl-lsch2/cpu.c                | 414 ++++++++++++++++++

Too much duplication. Please work with Alison/Prabhakar to move out the common
code in cpu.c.

York

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 10/16] ARMv8/ls1043ardb: Add LS1043ARDB board support
  2015-09-17  7:06 ` [U-Boot] [Patch v2 10/16] ARMv8/ls1043ardb: Add LS1043ARDB board support Gong Qianyu
@ 2015-09-21 17:27   ` York Sun
  0 siblings, 0 replies; 33+ messages in thread
From: York Sun @ 2015-09-21 17:27 UTC (permalink / raw)
  To: u-boot



On 09/17/2015 12:06 AM, Gong Qianyu wrote:
> From: Mingkai Hu <Mingkai.Hu@freescale.com>
> 
> LS1043ARDB Specification:
> -------------------------
> Memory subsystem:
>  * 2GByte DDR4 SDRAM (32bit but)

Do you mean "bus" here?

>  * 128 Mbyte NOR flash single-chip memory
>  * 512 Mbyte NAND flash
>  * 16 Mbyte high-speed SPI memory

Do you mean "SPI flash"?

>  * SD connector to interface with the SD memory card
> 
> Ethernet:
>  * XFI 10G port
>  * QSGMII with 4x 1G ports
>  * Two RGMII ports
> 
> PCIe:
>  * PCIe2 (Lanes C) to mini-PCIe slot
>  * PCIe3 (Lanes D) to PCIe slot
> 
> USB 3.0: two super speed USB 3.0 type A ports
> 
> UART: supports two UARTs up to 115200 bps for console
> 
> Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
> ---
>  V2:
>  Replaced ns_access.h with fsl_csu.h.

<snip>

> --- /dev/null
> +++ b/board/freescale/ls1043ardb/README
> @@ -0,0 +1,87 @@
> +Overview
> +--------
> +The LS1043A Reference Design Board (RDB) is a high-performance computing,
> +evaluation, and development platform that supports the QorIQ LS1043A
> +LayerScape Architecture processor. The LS1043ARDB provides SW development
> +platform for the Freescale LS1043A processor series, with a complete
> +debugging environment. The LS1043A RDB is lead-free and RoHS-compliant.
> +
> +LS1043A SoC Overview
> +--------------------
> +The LS1043A integrated multicore processor combines four ARM Cortex-A53
> +processor cores with datapath acceleration optimized for L2/3 packet
> +processing, single pass security offload and robust traffic management
> +and quality of service.
> +
> +The LS1043A SoC includes the following function and features:
> + - Four 64-bit ARM Cortex-A53 CPUs
> + - 1 MB unified L2 Cache
> + - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
> +   support
> + - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
> +   the following functions:
> +   - Packet parsing, classification, and distribution (FMan)
> +   - Queue management for scheduling, packet sequencing, and congestion
> +     management (QMan)
> +   - Hardware buffer management for buffer allocation and de-allocation (BMan)
> +   - Cryptography acceleration (SEC)
> + - Ethernet interfaces by FMan
> +   - Up to 1 x XFI supporting 10G interface
> +   - Up to 1 x QSGMII
> +   - Up to 4 x SGMII supporting 1000Mbps
> +   - Up to 2 x SGMII supporting 2500Mbps
> +   - Up to 2 x RGMII supporting 1000Mbps
> + - High-speed peripheral interfaces
> +   - Three PCIe 2.0 controllers, one supporting x4 operation
> +   - One serial ATA (SATA 3.0) controllers
> + - Additional peripheral interfaces
> +   - Three high-speed USB 3.0 controllers with integrated PHY
> +   - Enhanced secure digital host controller (eSDXC/eMMC)
> +   - Quad Serial Peripheral Interface (QSPI) Controller
> +   - Serial peripheral interface (SPI) controller
> +   - Four I2C controllers
> +   - Two DUARTs
> +   - Integrated flash controller supporting NAND and NOR flash
> + - QorIQ platform's trust architecture 2.1
> +
> + LS1043ARDB board Overview
> + -----------------------
> + - SERDES Connections, 4 lanes supporting:
> +      - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and
> +        standard PCIe card
> +      - QSGMII with x4 RJ45 connector
> +      - XFI with x1 RJ45 connector
> + - DDR Controller
> +     - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s
> + -IFC/Local Bus
> +    - One 128MB NOR flash 16-bit data bus
> +    - One 512 MB NAND flash with ECC support
> +    - CPLD connection
> + - USB 3.0
> +    - Two super speed USB 3.0 Type A ports
> + - SDHC: connects directly to a full SD/MMC slot
> + - DSPI: 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
> + - 4 I2C controllers
> + - UART
> +   - Two 4-pin serial ports at up to 115.2 Kbit/s
> +   - Two DB9 D-Type connectors supporting one Serial port each
> + - ARM JTAG support
> +
> +Memory map from core's view
> +----------------------------
> +Start Address	End Address	Description		Size
> +0x00_0000_0000	0x00_000F_FFFF	Secure Boot ROM		1MB
> +0x00_0100_0000	0x00_0FFF_FFFF	CCSRBAR			240MB
> +0x00_1000_0000	0x00_1000_FFFF	OCRAM0			64KB
> +0x00_1001_0000	0x00_1001_FFFF	OCRAM1			64KB
> +0x00_2000_0000	0x00_20FF_FFFF	DCSR			16MB
> +0x00_6000_0000	0x00_67FF_FFFF	IFC - NOR Flash		128MB
> +0x00_7E80_0000	0x00_7E80_FFFF	IFC - NAND Flash	64KB
> +0x00_7FB0_0000	0x00_7FB0_0FFF	IFC - FPGA		4KB
> +0x00_8000_0000	0x00_FFFF_FFFF	DRAM1			2GB
> +
> +Booting Options
> +---------------
> +a) NOR boot
> +b) NAND boot
> +c) SD boot

You don't have NAND or SD boot option with this patch yet. They were added
later. So you can update the README when you have those support.

<snip>
> +
> +#ifdef CONFIG_SYS_DDR_RAW_TIMING

Put a comment with DDR model number here.

> +dimm_params_t ddr_raw_timing = {
> +	.n_ranks = 1,
> +	.rank_density = 2147483648u,
> +	.capacity = 2147483648u,
> +	.primary_sdram_width = 32,
> +	.ec_sdram_width = 0,
> +	.registered_dimm = 0,
> +	.mirrored_dimm = 0,
> +	.n_row_addr = 15,
> +	.n_col_addr = 10,
> +	.bank_addr_bits = 0,
> +	.bank_group_bits = 2,
> +	.edc_config = 0,
> +	.burst_lengths_bitmask = 0x0c,
> +
> +	.tckmin_x_ps = 938,
> +	.tckmax_ps = 1500,
> +	.caslat_x = 0x000DFA00,
> +	.taa_ps = 13500,
> +	.trcd_ps = 13500,
> +	.trp_ps = 13500,
> +	.tras_ps = 33000,
> +	.trc_ps = 46500,
> +	.trfc1_ps = 260000,
> +	.trfc2_ps = 160000,
> +	.trfc4_ps = 110000,
> +	.tfaw_ps = 21000,
> +	.trrds_ps = 3700,
> +	.trrdl_ps = 5300,
> +	.tccdl_ps = 5355,
> +	.refresh_rate_ps = 7800000,
> +	.dq_mapping[0] = 0x0,
> +	.dq_mapping[1] = 0x0,
> +	.dq_mapping[2] = 0x0,
> +	.dq_mapping[3] = 0x0,
> +	.dq_mapping[4] = 0x0,
> +	.dq_mapping[5] = 0x0,
> +	.dq_mapping[6] = 0x0,
> +	.dq_mapping[7] = 0x0,
> +	.dq_mapping[8] = 0x0,
> +	.dq_mapping[9] = 0x0,
> +	.dq_mapping[10] = 0x0,
> +	.dq_mapping[11] = 0x0,
> +	.dq_mapping[12] = 0x0,
> +	.dq_mapping[13] = 0x0,
> +	.dq_mapping[14] = 0x0,
> +	.dq_mapping[15] = 0x0,
> +	.dq_mapping[16] = 0x0,
> +	.dq_mapping[17] = 0x0,
> +	.dq_mapping_ors = 0,
> +};
> +

You may want to try to use -M -C when generating the patch, to see if the patch
can be smaller. I have a feeling many files are copy-n-paste with some modification.

York

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 16/16] armv8/ls1043ardb: Add cpld command to boot from sd
  2015-09-17  7:06 ` [U-Boot] [Patch v2 16/16] armv8/ls1043ardb: Add cpld command to boot from sd Gong Qianyu
@ 2015-09-21 17:27   ` York Sun
  0 siblings, 0 replies; 33+ messages in thread
From: York Sun @ 2015-09-21 17:27 UTC (permalink / raw)
  To: u-boot



On 09/17/2015 12:06 AM, Gong Qianyu wrote:
> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
> ---
>  board/freescale/ls1043ardb/cpld.c | 17 +++++++++++++++++
>  board/freescale/ls1043ardb/cpld.h |  1 +
>  2 files changed, 18 insertions(+)

Squash this patch with SD boot patch.

York

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 12/16] armv8/ls1043ardb: Add cpld command to boot from nand
  2015-09-17  7:06 ` [U-Boot] [Patch v2 12/16] armv8/ls1043ardb: Add cpld command to boot from nand Gong Qianyu
@ 2015-09-21 17:27   ` York Sun
  0 siblings, 0 replies; 33+ messages in thread
From: York Sun @ 2015-09-21 17:27 UTC (permalink / raw)
  To: u-boot



On 09/17/2015 12:06 AM, Gong Qianyu wrote:
> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
> ---
>  board/freescale/ls1043ardb/cpld.c | 18 ++++++++++++++++++
>  board/freescale/ls1043ardb/cpld.h |  1 +
>  2 files changed, 19 insertions(+)
> 

Squash this patch with nand boot patch.

York

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 08/16] net/fm: fix compile warnings for 64-bit platform
  2015-09-17 18:13   ` Scott Wood
@ 2015-09-25  2:22     ` Hou Zhiqiang
  2015-09-25  2:33       ` Scott Wood
  0 siblings, 1 reply; 33+ messages in thread
From: Hou Zhiqiang @ 2015-09-25  2:22 UTC (permalink / raw)
  To: u-boot



> -----Original Message-----
> From: Wood Scott-B07421
> Sent: 2015?9?18? 2:14
> To: Gong Qianyu-B52263
> Cc: u-boot at lists.denx.de; Hu Mingkai-B21284; Sun York-R58495; Hou
> Zhiqiang-B48286; Song Wenbin-B53747; Xie Shaohui-B21989; Wood Scott-
> B07421
> Subject: Re: [Patch v2 08/16] net/fm: fix compile warnings for 64-bit
> platform
> 
> On Thu, 2015-09-17 at 15:06 +0800, Gong Qianyu wrote:
> > This patch fixes such compile warnings:
> >
> > drivers/net/fm/eth.c: In function 'fm_eth_recv':
> > drivers/net/fm/eth.c:549:11: warning: cast to pointer from integer of
> > different size [-Wint-to-pointer-cast]
> >       data = (u8 *)in_be32(&rxbd->buf_ptr_lo);
> > drivers/net/fm/fm.c: In function 'fm_muram_alloc':
> > drivers/net/fm/fm.c:52:9: warning: cast to pointer from integer of
> > different size [-Wint-to-pointer-cast]
> >       memset((void *)ret, 0, size);
> > drivers/net/fm/fm.c: In function 'fm_init_muram':
> > drivers/net/fm/fm.c:59:13: warning: cast from pointer to integer of
> > different size [-Wpointer-to-int-cast]
> >       u32 base = (u32)reg;
> >
> > Just make the cast explicit for them.
> >
> > Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
> > ---
> >  drivers/net/fm/eth.c | 31 ++++++++++++++++---------------
> > drivers/net/fm/fm.c  |  4 ++--
> >  2 files changed, 18 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index
> > 12eb9b8..6ef0afb 100644
> > --- a/drivers/net/fm/eth.c
> > +++ b/drivers/net/fm/eth.c
> > @@ -120,12 +120,12 @@ static int tgec_is_fibre(struct eth_device *dev)
> >
> >  static u16 muram_readw(u16 *addr)
> >  {
> > -     u32 base = (u32)addr & ~0x3;
> > +     ulong base = (ulong)addr & ~0x3;
> 
> This will still truncate the address at 32 bits.  It needs to be ~0x3UL.
> 
> 
> >       u32 val32 = in_be32((u32 *)base);
> >       int byte_pos;
> >       u16 ret;
> >
> > -     byte_pos = (u32)addr & 0x3;
> > +     byte_pos = (ulong)addr & 0x3;
> >       if (byte_pos)
> >               ret = (u16)(val32 & 0x0000ffff);
> >       else
> > @@ -136,12 +136,12 @@ static u16 muram_readw(u16 *addr)
> >
> >  static void muram_writew(u16 *addr, u16 val)  {
> > -     u32 base = (u32)addr & ~0x3;
> > +     ulong base = (ulong)addr & ~0x3;
> >       u32 org32 = in_be32((u32 *)base);
> >       u32 val32;
> >       int byte_pos;
> >
> > -     byte_pos = (u32)addr & 0x3;
> > +     byte_pos = (ulong)addr & 0x3;
> >       if (byte_pos)
> >               val32 = (org32 & 0xffff0000) | val;
> >       else
> > @@ -217,12 +217,12 @@ static int fm_eth_rx_port_parameter_init(struct
> > fm_eth *fm_eth)
> >       int i;
> >
> >       /* alloc global parameter ram at MURAM */
> > -     pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth-
> >fm_index,
> > -             FM_PRAM_SIZE, FM_PRAM_ALIGN);
> > +     pram = (struct fm_port_global_pram *)(ulong)fm_muram_alloc(
> > +                     fm_eth->fm_index, FM_PRAM_SIZE, FM_PRAM_ALIGN);
> 
> Make fm_muram_alloc() return a pointer instead.  If muram were >= 4 GiB
> the above would fail.
> 
 
The muram is a region included in CCSR.
So does we take muram >= 4GiB into account make sense?

> >       fm_eth->rx_pram = pram;
> >
> >       /* parameter page offset to MURAM */
> > -     pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
> > +     pram_page_offset = (u32)(ulong)pram -
> > + fm_muram_base(fm_eth->fm_index);
> 
> Get rid of the u32 cast -- again, if the muram base were above >= 4 GiB
> this would fail because you're dropping the high bits before the
> subtraction rather than after.
> 
> >
> >       /* enable global mode- snooping data buffers and BDs */
> >       out_be32(&pram->mode, PRAM_MODE_GLOBAL); @@ -258,7 +258,8 @@
> > static int fm_eth_rx_port_parameter_init(struct fm_eth
> > *fm_eth)
> >               muram_writew(&rxbd->status, RxBD_EMPTY);
> >               muram_writew(&rxbd->len, 0);
> >               muram_writew(&rxbd->buf_ptr_hi, 0);
> > -             out_be32(&rxbd->buf_ptr_lo, (u32)rx_buf_pool + i *
> MAX_RXBUF_LEN);
> > +             out_be32(&rxbd->buf_ptr_lo, (u32)(ulong)rx_buf_pool +
> > +                                                     i *
> > + MAX_RXBUF_LEN);
> >               rxbd++;
> 
> Use virt_to_phys() and lower_32_bits().  Is there a "hi" register to
> handle the upper 32 bits?
> 
> Likewise elsewhere.  Don't just apply the minimum bandage to get rid of
> the warning.  Make the code actually be 64-bit clean.
> 

Thanks,
Zhiqiang

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 08/16] net/fm: fix compile warnings for 64-bit platform
  2015-09-25  2:22     ` Hou Zhiqiang
@ 2015-09-25  2:33       ` Scott Wood
  2015-09-25  3:49         ` Hou Zhiqiang
  0 siblings, 1 reply; 33+ messages in thread
From: Scott Wood @ 2015-09-25  2:33 UTC (permalink / raw)
  To: u-boot

On Thu, 2015-09-24 at 21:22 -0500, Hou Zhiqiang-B48286 wrote:
> 
> > -----Original Message-----
> > From: Wood Scott-B07421
> > Sent: 2015?9?18? 2:14
> > To: Gong Qianyu-B52263
> > Cc: u-boot at lists.denx.de; Hu Mingkai-B21284; Sun York-R58495; Hou
> > Zhiqiang-B48286; Song Wenbin-B53747; Xie Shaohui-B21989; Wood Scott-
> > B07421
> > Subject: Re: [Patch v2 08/16] net/fm: fix compile warnings for 64-bit
> > platform
> > 
> > On Thu, 2015-09-17 at 15:06 +0800, Gong Qianyu wrote:
> > > This patch fixes such compile warnings:
> > > 
> > > drivers/net/fm/eth.c: In function 'fm_eth_recv':
> > > drivers/net/fm/eth.c:549:11: warning: cast to pointer from integer of
> > > different size [-Wint-to-pointer-cast]
> > >       data = (u8 *)in_be32(&rxbd->buf_ptr_lo);
> > > drivers/net/fm/fm.c: In function 'fm_muram_alloc':
> > > drivers/net/fm/fm.c:52:9: warning: cast to pointer from integer of
> > > different size [-Wint-to-pointer-cast]
> > >       memset((void *)ret, 0, size);
> > > drivers/net/fm/fm.c: In function 'fm_init_muram':
> > > drivers/net/fm/fm.c:59:13: warning: cast from pointer to integer of
> > > different size [-Wpointer-to-int-cast]
> > >       u32 base = (u32)reg;
> > > 
> > > Just make the cast explicit for them.
> > > 
> > > Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
> > > ---
> > >  drivers/net/fm/eth.c | 31 ++++++++++++++++---------------
> > > drivers/net/fm/fm.c  |  4 ++--
> > >  2 files changed, 18 insertions(+), 17 deletions(-)
> > > 
> > > diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index
> > > 12eb9b8..6ef0afb 100644
> > > --- a/drivers/net/fm/eth.c
> > > +++ b/drivers/net/fm/eth.c
> > > @@ -120,12 +120,12 @@ static int tgec_is_fibre(struct eth_device *dev)
> > > 
> > >  static u16 muram_readw(u16 *addr)
> > >  {
> > > -     u32 base = (u32)addr & ~0x3;
> > > +     ulong base = (ulong)addr & ~0x3;
> > 
> > This will still truncate the address at 32 bits.  It needs to be ~0x3UL.
> > 
> > 
> > >       u32 val32 = in_be32((u32 *)base);
> > >       int byte_pos;
> > >       u16 ret;
> > > 
> > > -     byte_pos = (u32)addr & 0x3;
> > > +     byte_pos = (ulong)addr & 0x3;
> > >       if (byte_pos)
> > >               ret = (u16)(val32 & 0x0000ffff);
> > >       else
> > > @@ -136,12 +136,12 @@ static u16 muram_readw(u16 *addr)
> > > 
> > >  static void muram_writew(u16 *addr, u16 val)  {
> > > -     u32 base = (u32)addr & ~0x3;
> > > +     ulong base = (ulong)addr & ~0x3;
> > >       u32 org32 = in_be32((u32 *)base);
> > >       u32 val32;
> > >       int byte_pos;
> > > 
> > > -     byte_pos = (u32)addr & 0x3;
> > > +     byte_pos = (ulong)addr & 0x3;
> > >       if (byte_pos)
> > >               val32 = (org32 & 0xffff0000) | val;
> > >       else
> > > @@ -217,12 +217,12 @@ static int fm_eth_rx_port_parameter_init(struct
> > > fm_eth *fm_eth)
> > >       int i;
> > > 
> > >       /* alloc global parameter ram at MURAM */
> > > -     pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth-
> > > fm_index,
> > > -             FM_PRAM_SIZE, FM_PRAM_ALIGN);
> > > +     pram = (struct fm_port_global_pram *)(ulong)fm_muram_alloc(
> > > +                     fm_eth->fm_index, FM_PRAM_SIZE, FM_PRAM_ALIGN);
> > 
> > Make fm_muram_alloc() return a pointer instead.  If muram were >= 4 GiB
> > the above would fail.
> > 
>  
> The muram is a region included in CCSR.
> So does we take muram >= 4GiB into account make sense?

The fact that currently, we run U-Boot as 32-bit on platforms where CCSR is 
>= 4GiB is not a good excuse to be sloppy with types.

-Scott

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 08/16] net/fm: fix compile warnings for 64-bit platform
  2015-09-25  2:33       ` Scott Wood
@ 2015-09-25  3:49         ` Hou Zhiqiang
  0 siblings, 0 replies; 33+ messages in thread
From: Hou Zhiqiang @ 2015-09-25  3:49 UTC (permalink / raw)
  To: u-boot



> -----Original Message-----
> From: Wood Scott-B07421
> Sent: 2015?9?25? 10:34
> To: Hou Zhiqiang-B48286
> Cc: Gong Qianyu-B52263; u-boot at lists.denx.de; Hu Mingkai-B21284; Sun
> York-R58495; Song Wenbin-B53747; Xie Shaohui-B21989
> Subject: Re: [Patch v2 08/16] net/fm: fix compile warnings for 64-bit
> platform
> 
> On Thu, 2015-09-24 at 21:22 -0500, Hou Zhiqiang-B48286 wrote:
> >
> > > -----Original Message-----
> > > From: Wood Scott-B07421
> > > Sent: 2015?9?18? 2:14
> > > To: Gong Qianyu-B52263
> > > Cc: u-boot at lists.denx.de; Hu Mingkai-B21284; Sun York-R58495; Hou
> > > Zhiqiang-B48286; Song Wenbin-B53747; Xie Shaohui-B21989; Wood Scott-
> > > B07421
> > > Subject: Re: [Patch v2 08/16] net/fm: fix compile warnings for
> > > 64-bit platform
> > >
> > > On Thu, 2015-09-17 at 15:06 +0800, Gong Qianyu wrote:
> > > > This patch fixes such compile warnings:
> > > >
> > > > drivers/net/fm/eth.c: In function 'fm_eth_recv':
> > > > drivers/net/fm/eth.c:549:11: warning: cast to pointer from integer
> > > > of different size [-Wint-to-pointer-cast]
> > > >       data = (u8 *)in_be32(&rxbd->buf_ptr_lo);
> > > > drivers/net/fm/fm.c: In function 'fm_muram_alloc':
> > > > drivers/net/fm/fm.c:52:9: warning: cast to pointer from integer of
> > > > different size [-Wint-to-pointer-cast]
> > > >       memset((void *)ret, 0, size);
> > > > drivers/net/fm/fm.c: In function 'fm_init_muram':
> > > > drivers/net/fm/fm.c:59:13: warning: cast from pointer to integer
> > > > of different size [-Wpointer-to-int-cast]
> > > >       u32 base = (u32)reg;
> > > >
> > > > Just make the cast explicit for them.
> > > >
> > > > Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
> > > > ---
> > > >  drivers/net/fm/eth.c | 31 ++++++++++++++++---------------
> > > > drivers/net/fm/fm.c  |  4 ++--
> > > >  2 files changed, 18 insertions(+), 17 deletions(-)
> > > >
> > > > diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index
> > > > 12eb9b8..6ef0afb 100644
> > > > --- a/drivers/net/fm/eth.c
> > > > +++ b/drivers/net/fm/eth.c
> > > > @@ -120,12 +120,12 @@ static int tgec_is_fibre(struct eth_device
> > > > *dev)
> > > >
> > > >  static u16 muram_readw(u16 *addr)  {
> > > > -     u32 base = (u32)addr & ~0x3;
> > > > +     ulong base = (ulong)addr & ~0x3;
> > >
> > > This will still truncate the address at 32 bits.  It needs to be
> ~0x3UL.
> > >
> > >
> > > >       u32 val32 = in_be32((u32 *)base);
> > > >       int byte_pos;
> > > >       u16 ret;
> > > >
> > > > -     byte_pos = (u32)addr & 0x3;
> > > > +     byte_pos = (ulong)addr & 0x3;
> > > >       if (byte_pos)
> > > >               ret = (u16)(val32 & 0x0000ffff);
> > > >       else
> > > > @@ -136,12 +136,12 @@ static u16 muram_readw(u16 *addr)
> > > >
> > > >  static void muram_writew(u16 *addr, u16 val)  {
> > > > -     u32 base = (u32)addr & ~0x3;
> > > > +     ulong base = (ulong)addr & ~0x3;
> > > >       u32 org32 = in_be32((u32 *)base);
> > > >       u32 val32;
> > > >       int byte_pos;
> > > >
> > > > -     byte_pos = (u32)addr & 0x3;
> > > > +     byte_pos = (ulong)addr & 0x3;
> > > >       if (byte_pos)
> > > >               val32 = (org32 & 0xffff0000) | val;
> > > >       else
> > > > @@ -217,12 +217,12 @@ static int
> > > > fm_eth_rx_port_parameter_init(struct
> > > > fm_eth *fm_eth)
> > > >       int i;
> > > >
> > > >       /* alloc global parameter ram at MURAM */
> > > > -     pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth-
> > > > fm_index,
> > > > -             FM_PRAM_SIZE, FM_PRAM_ALIGN);
> > > > +     pram = (struct fm_port_global_pram *)(ulong)fm_muram_alloc(
> > > > +                     fm_eth->fm_index, FM_PRAM_SIZE,
> > > > + FM_PRAM_ALIGN);
> > >
> > > Make fm_muram_alloc() return a pointer instead.  If muram were >= 4
> > > GiB the above would fail.
> > >
> >
> > The muram is a region included in CCSR.
> > So does we take muram >= 4GiB into account make sense?
> 
> The fact that currently, we run U-Boot as 32-bit on platforms where CCSR
> is
> >= 4GiB is not a good excuse to be sloppy with types.
> 

ok.

Thanks,
Zhiqiang

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 07/16] net/fm: fix MDIO controller base on FMAN2
  2015-09-18  5:13       ` Scott Wood
@ 2015-09-25 10:51         ` Hu Vincent
  0 siblings, 0 replies; 33+ messages in thread
From: Hu Vincent @ 2015-09-25 10:51 UTC (permalink / raw)
  To: u-boot



> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Friday, September 18, 2015 1:13 PM
> To: Xie Shaohui-B21989
> Cc: Gong Qianyu-B52263; u-boot at lists.denx.de; Hu Mingkai-B21284; Sun
> York-R58495; Hou Zhiqiang-B48286; Song Wenbin-B53747
> Subject: Re: [Patch v2 07/16] net/fm: fix MDIO controller base on FMAN2
> 
> > > doc/README.fsl-dpaa says that CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
> > > is for newer SoCs.  Presumably this patch is for ls1043a -- is that
> > > not considered a newer SoC?  Or does the README need to be fixed?
> > [S.H] Yes, this is for LS1043A. LS1043A has one FMAN same as T2080.
> > A new SoC but has an old DPAA.
> 
> So maybe the README should be changed to more accurately talk about FMan
> versions?
> 
Thanks, we will change the README to make it clear.

Thanks,
Mingkai

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 09/16] ARMv8/FSL_LSCH2: Add FSL_LSCH2 SoC
  2015-09-21 17:27   ` York Sun
@ 2015-09-25 12:28     ` Hu Vincent
  2015-09-25 14:53       ` York Sun
  0 siblings, 1 reply; 33+ messages in thread
From: Hu Vincent @ 2015-09-25 12:28 UTC (permalink / raw)
  To: u-boot



> -----Original Message-----
> From: Sun York-R58495
> Sent: Tuesday, September 22, 2015 1:27 AM
> To: Gong Qianyu-B52263; u-boot at lists.denx.de
> Cc: Hu Mingkai-B21284; Sun York-R58495; Hou Zhiqiang-B48286; Song Wenbin-
> B53747; Xie Shaohui-B21989; Wood Scott-B07421; Li Yang-Leo-R58472
> Subject: Re: [Patch v2 09/16] ARMv8/FSL_LSCH2: Add FSL_LSCH2 SoC
> 
> 
> 
> On 09/17/2015 12:06 AM, Gong Qianyu wrote:
> > From: Mingkai Hu <Mingkai.Hu@freescale.com>
> >
> > Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
> > ARMv8 cores and 2rd generation of Chassis.
> >
> > Signed-off-by: Li Yang <leoli@freescale.com>
> > Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
> > Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
> > Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
> > ---
> > V2:
> > remove FSL_LS102xA_DEVDISR3_PCIE from immap_lsch2.h
> >
> >  arch/arm/cpu/armv8/Makefile                       |   1 +
> >  arch/arm/cpu/armv8/fsl-lsch2/Makefile             |  12 +
> >  arch/arm/cpu/armv8/fsl-lsch2/README               |  10 +
> >  arch/arm/cpu/armv8/fsl-lsch2/cpu.c                | 414
> ++++++++++++++++++
> 
> Too much duplication. Please work with Alison/Prabhakar to move out the
> common code in cpu.c.
> 

I agree, there are too much duplications between lsch2 and lsch3:

arch/arm/cpu/armv8/fsl-lsch*
arch/arm/include/asm/arch-fsl-lsch*

I am considering to consolidate the code between lsch2 and lsch3 using arch-layerscape. The basic idea is to add the following directory for ARMv8 layerscape for the common files and use CONFIG_FSL_LSCH2/ CONFIG_FSL_LSCH3 to differentiate the difference between these two chassis in the same file if necessary.

arch/arm/cpu/armv8/fsl-layerscape
arch/arm/include/asm/arch-fsl-layerscape/

what is your suggestion?

We will send out version 3 to address the other comments and use it as the base for such consolidation.

Thanks,
Mingkai

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 09/16] ARMv8/FSL_LSCH2: Add FSL_LSCH2 SoC
  2015-09-25 12:28     ` Hu Vincent
@ 2015-09-25 14:53       ` York Sun
  2015-09-27  4:10         ` Kushwaha Prabhakar
  0 siblings, 1 reply; 33+ messages in thread
From: York Sun @ 2015-09-25 14:53 UTC (permalink / raw)
  To: u-boot



On 09/25/2015 05:28 AM, Hu Mingkai-B21284 wrote:
> 
> 
>> -----Original Message-----
>> From: Sun York-R58495
>> Sent: Tuesday, September 22, 2015 1:27 AM
>> To: Gong Qianyu-B52263; u-boot at lists.denx.de
>> Cc: Hu Mingkai-B21284; Sun York-R58495; Hou Zhiqiang-B48286; Song Wenbin-
>> B53747; Xie Shaohui-B21989; Wood Scott-B07421; Li Yang-Leo-R58472
>> Subject: Re: [Patch v2 09/16] ARMv8/FSL_LSCH2: Add FSL_LSCH2 SoC
>>
>>
>>
>> On 09/17/2015 12:06 AM, Gong Qianyu wrote:
>>> From: Mingkai Hu <Mingkai.Hu@freescale.com>
>>>
>>> Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
>>> ARMv8 cores and 2rd generation of Chassis.
>>>
>>> Signed-off-by: Li Yang <leoli@freescale.com>
>>> Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
>>> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
>>> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
>>> ---
>>> V2:
>>> remove FSL_LS102xA_DEVDISR3_PCIE from immap_lsch2.h
>>>
>>>  arch/arm/cpu/armv8/Makefile                       |   1 +
>>>  arch/arm/cpu/armv8/fsl-lsch2/Makefile             |  12 +
>>>  arch/arm/cpu/armv8/fsl-lsch2/README               |  10 +
>>>  arch/arm/cpu/armv8/fsl-lsch2/cpu.c                | 414
>> ++++++++++++++++++
>>
>> Too much duplication. Please work with Alison/Prabhakar to move out the
>> common code in cpu.c.
>>
> 
> I agree, there are too much duplications between lsch2 and lsch3:
> 
> arch/arm/cpu/armv8/fsl-lsch*
> arch/arm/include/asm/arch-fsl-lsch*
> 
> I am considering to consolidate the code between lsch2 and lsch3 using arch-layerscape. The basic idea is to add the following directory for ARMv8 layerscape for the common files and use CONFIG_FSL_LSCH2/ CONFIG_FSL_LSCH3 to differentiate the difference between these two chassis in the same file if necessary.
> 
> arch/arm/cpu/armv8/fsl-layerscape
> arch/arm/include/asm/arch-fsl-layerscape/
> 
> what is your suggestion?
> 

I think it is worth a try.

York

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 09/16] ARMv8/FSL_LSCH2: Add FSL_LSCH2 SoC
  2015-09-25 14:53       ` York Sun
@ 2015-09-27  4:10         ` Kushwaha Prabhakar
  2015-09-28  7:23           ` Hu Vincent
  0 siblings, 1 reply; 33+ messages in thread
From: Kushwaha Prabhakar @ 2015-09-27  4:10 UTC (permalink / raw)
  To: u-boot


> -----Original Message-----
> From: U-Boot [mailto:u-boot-bounces at lists.denx.de] On Behalf Of York Sun
> Sent: Friday, September 25, 2015 8:23 PM
> To: Hu Mingkai-B21284 <Mingkai.Hu@freescale.com>; Gong Qianyu-B52263
> <Qianyu.Gong@freescale.com>; u-boot at lists.denx.de
> Cc: Wood Scott-B07421 <scottwood@freescale.com>; Li Yang-Leo-R58472
> <LeoLi@freescale.com>; Hou Zhiqiang-B48286 <B48286@freescale.com>;
> Song Wenbin-B53747 <Wenbin.Song@freescale.com>
> Subject: Re: [U-Boot] [Patch v2 09/16] ARMv8/FSL_LSCH2: Add FSL_LSCH2
> SoC
> 
> 
> 
> On 09/25/2015 05:28 AM, Hu Mingkai-B21284 wrote:
> >
> >
> >> -----Original Message-----
> >> From: Sun York-R58495
> >> Sent: Tuesday, September 22, 2015 1:27 AM
> >> To: Gong Qianyu-B52263; u-boot at lists.denx.de
> >> Cc: Hu Mingkai-B21284; Sun York-R58495; Hou Zhiqiang-B48286; Song
> >> Wenbin- B53747; Xie Shaohui-B21989; Wood Scott-B07421; Li
> >> Yang-Leo-R58472
> >> Subject: Re: [Patch v2 09/16] ARMv8/FSL_LSCH2: Add FSL_LSCH2 SoC
> >>
> >>
> >>
> >> On 09/17/2015 12:06 AM, Gong Qianyu wrote:
> >>> From: Mingkai Hu <Mingkai.Hu@freescale.com>
> >>>
> >>> Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
> >>> ARMv8 cores and 2rd generation of Chassis.
> >>>
> >>> Signed-off-by: Li Yang <leoli@freescale.com>
> >>> Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
> >>> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
> >>> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
> >>> ---
> >>> V2:
> >>> remove FSL_LS102xA_DEVDISR3_PCIE from immap_lsch2.h
> >>>
> >>>  arch/arm/cpu/armv8/Makefile                       |   1 +
> >>>  arch/arm/cpu/armv8/fsl-lsch2/Makefile             |  12 +
> >>>  arch/arm/cpu/armv8/fsl-lsch2/README               |  10 +
> >>>  arch/arm/cpu/armv8/fsl-lsch2/cpu.c                | 414
> >> ++++++++++++++++++
> >>
> >> Too much duplication. Please work with Alison/Prabhakar to move out
> >> the common code in cpu.c.
> >>
> >
> > I agree, there are too much duplications between lsch2 and lsch3:
> >
> > arch/arm/cpu/armv8/fsl-lsch*
> > arch/arm/include/asm/arch-fsl-lsch*
> >
> > I am considering to consolidate the code between lsch2 and lsch3 using
> arch-layerscape. The basic idea is to add the following directory for ARMv8
> layerscape for the common files and use CONFIG_FSL_LSCH2/
> CONFIG_FSL_LSCH3 to differentiate the difference between these two
> chassis in the same file if necessary.
> >
> > arch/arm/cpu/armv8/fsl-layerscape
> > arch/arm/include/asm/arch-fsl-layerscape/
> >
> > what is your suggestion?

Other than CONFIG_FSL_LSCH2 and CONFIG_FSL_LSCH3, we should also have CONFIG_FSL_LAYERSCAPE to enabled common code.

--prabhakar

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [U-Boot] [Patch v2 09/16] ARMv8/FSL_LSCH2: Add FSL_LSCH2 SoC
  2015-09-27  4:10         ` Kushwaha Prabhakar
@ 2015-09-28  7:23           ` Hu Vincent
  0 siblings, 0 replies; 33+ messages in thread
From: Hu Vincent @ 2015-09-28  7:23 UTC (permalink / raw)
  To: u-boot



> -----Original Message-----
> From: Kushwaha Prabhakar-B32579
> Sent: Sunday, September 27, 2015 12:11 PM
> To: Sun York-R58495; Hu Mingkai-B21284; Gong Qianyu-B52263; u-
> boot at lists.denx.de
> Cc: Wood Scott-B07421; Li Yang-Leo-R58472; Hou Zhiqiang-B48286; Song
> Wenbin-B53747
> Subject: RE: [U-Boot] [Patch v2 09/16] ARMv8/FSL_LSCH2: Add FSL_LSCH2 SoC
> 
> 
> > -----Original Message-----
> > From: U-Boot [mailto:u-boot-bounces at lists.denx.de] On Behalf Of York
> > Sun
> > Sent: Friday, September 25, 2015 8:23 PM
> > To: Hu Mingkai-B21284 <Mingkai.Hu@freescale.com>; Gong Qianyu-B52263
> > <Qianyu.Gong@freescale.com>; u-boot at lists.denx.de
> > Cc: Wood Scott-B07421 <scottwood@freescale.com>; Li Yang-Leo-R58472
> > <LeoLi@freescale.com>; Hou Zhiqiang-B48286 <B48286@freescale.com>;
> > Song Wenbin-B53747 <Wenbin.Song@freescale.com>
> > Subject: Re: [U-Boot] [Patch v2 09/16] ARMv8/FSL_LSCH2: Add FSL_LSCH2
> > SoC
> >
> >
> >
> > On 09/25/2015 05:28 AM, Hu Mingkai-B21284 wrote:
> > >
> > >
> > >> -----Original Message-----
> > >> From: Sun York-R58495
> > >> Sent: Tuesday, September 22, 2015 1:27 AM
> > >> To: Gong Qianyu-B52263; u-boot at lists.denx.de
> > >> Cc: Hu Mingkai-B21284; Sun York-R58495; Hou Zhiqiang-B48286; Song
> > >> Wenbin- B53747; Xie Shaohui-B21989; Wood Scott-B07421; Li
> > >> Yang-Leo-R58472
> > >> Subject: Re: [Patch v2 09/16] ARMv8/FSL_LSCH2: Add FSL_LSCH2 SoC
> > >>
> > >>
> > >>
> > >> On 09/17/2015 12:06 AM, Gong Qianyu wrote:
> > >>> From: Mingkai Hu <Mingkai.Hu@freescale.com>
> > >>>
> > >>> Freescale LayerScape with Chassis Generation 2 is a set of SoCs
> > >>> with
> > >>> ARMv8 cores and 2rd generation of Chassis.
> > >>>
> > >>> Signed-off-by: Li Yang <leoli@freescale.com>
> > >>> Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
> > >>> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
> > >>> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
> > >>> ---
> > >>> V2:
> > >>> remove FSL_LS102xA_DEVDISR3_PCIE from immap_lsch2.h
> > >>>
> > >>>  arch/arm/cpu/armv8/Makefile                       |   1 +
> > >>>  arch/arm/cpu/armv8/fsl-lsch2/Makefile             |  12 +
> > >>>  arch/arm/cpu/armv8/fsl-lsch2/README               |  10 +
> > >>>  arch/arm/cpu/armv8/fsl-lsch2/cpu.c                | 414
> > >> ++++++++++++++++++
> > >>
> > >> Too much duplication. Please work with Alison/Prabhakar to move out
> > >> the common code in cpu.c.
> > >>
> > >
> > > I agree, there are too much duplications between lsch2 and lsch3:
> > >
> > > arch/arm/cpu/armv8/fsl-lsch*
> > > arch/arm/include/asm/arch-fsl-lsch*
> > >
> > > I am considering to consolidate the code between lsch2 and lsch3
> > > using
> > arch-layerscape. The basic idea is to add the following directory for
> > ARMv8 layerscape for the common files and use CONFIG_FSL_LSCH2/
> > CONFIG_FSL_LSCH3 to differentiate the difference between these two
> > chassis in the same file if necessary.
> > >
> > > arch/arm/cpu/armv8/fsl-layerscape
> > > arch/arm/include/asm/arch-fsl-layerscape/
> > >
> > > what is your suggestion?
> 
> Other than CONFIG_FSL_LSCH2 and CONFIG_FSL_LSCH3, we should also have
> CONFIG_FSL_LAYERSCAPE to enabled common code.
> 
Sure. We need a macro to enable the common code.
Thanks,
Mingkai

^ permalink raw reply	[flat|nested] 33+ messages in thread

end of thread, other threads:[~2015-09-28  7:23 UTC | newest]

Thread overview: 33+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-09-17  7:06 [U-Boot] [Patch v2 04/16] net/fm: bug fix when CONFIG_PHYLIB not defined Gong Qianyu
2015-09-17  7:06 ` [U-Boot] [Patch v2 05/16] net: Move some header files to include/ Gong Qianyu
2015-09-17 18:06   ` Scott Wood
2015-09-17  7:06 ` [U-Boot] [Patch v2 06/16] net/fm: Add QSGMII PCS init Gong Qianyu
2015-09-17  7:06 ` [U-Boot] [Patch v2 07/16] net/fm: fix MDIO controller base on FMAN2 Gong Qianyu
2015-09-17 18:04   ` Scott Wood
2015-09-18  3:49     ` Shaohui Xie
2015-09-18  5:13       ` Scott Wood
2015-09-25 10:51         ` Hu Vincent
2015-09-17  7:06 ` [U-Boot] [Patch v2 08/16] net/fm: fix compile warnings for 64-bit platform Gong Qianyu
2015-09-17 18:13   ` Scott Wood
2015-09-25  2:22     ` Hou Zhiqiang
2015-09-25  2:33       ` Scott Wood
2015-09-25  3:49         ` Hou Zhiqiang
2015-09-17  7:06 ` [U-Boot] [Patch v2 09/16] ARMv8/FSL_LSCH2: Add FSL_LSCH2 SoC Gong Qianyu
2015-09-21 17:27   ` York Sun
2015-09-25 12:28     ` Hu Vincent
2015-09-25 14:53       ` York Sun
2015-09-27  4:10         ` Kushwaha Prabhakar
2015-09-28  7:23           ` Hu Vincent
2015-09-17  7:06 ` [U-Boot] [Patch v2 10/16] ARMv8/ls1043ardb: Add LS1043ARDB board support Gong Qianyu
2015-09-21 17:27   ` York Sun
2015-09-17  7:06 ` [U-Boot] [Patch v2 11/16] armv8/ls1043ardb: Add nand boot support Gong Qianyu
2015-09-17 20:16   ` Scott Wood
2015-09-18  3:36     ` Gong Q.Y.
2015-09-18  5:14       ` Scott Wood
2015-09-17  7:06 ` [U-Boot] [Patch v2 12/16] armv8/ls1043ardb: Add cpld command to boot from nand Gong Qianyu
2015-09-21 17:27   ` York Sun
2015-09-17  7:06 ` [U-Boot] [Patch v2 13/16] armv8/ls1043a: Add Fman support Gong Qianyu
2015-09-17  7:06 ` [U-Boot] [Patch v2 14/16] armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardb Gong Qianyu
2015-09-17  7:06 ` [U-Boot] [Patch v2 15/16] armv8/ls1043ardb: Add sd boot support Gong Qianyu
2015-09-17  7:06 ` [U-Boot] [Patch v2 16/16] armv8/ls1043ardb: Add cpld command to boot from sd Gong Qianyu
2015-09-21 17:27   ` York Sun

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox