From: Scott Wood <scottwood@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [Patch V2 1/4] pci/layerscape: add support for LS1043A PCIe LUT register access
Date: Wed, 4 Nov 2015 17:45:28 -0600 [thread overview]
Message-ID: <1446680728.12676.28.camel@freescale.com> (raw)
In-Reply-To: <1446462947-44185-2-git-send-email-Qianyu.Gong@freescale.com>
On Mon, 2015-11-02 at 19:15 +0800, Gong Qianyu wrote:
> diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
> index 4cee038..8471678 100644
> --- a/drivers/pci/pcie_layerscape.c
> +++ b/drivers/pci/pcie_layerscape.c
> @@ -13,6 +13,7 @@
> #include <malloc.h>
> #ifdef CONFIG_FSL_LAYERSCAPE
> #include <asm/arch/fdt.h>
> +#include <asm/arch/soc.h>
> #endif
>
> #ifndef CONFIG_SYS_PCI_MEMORY_BUS
> @@ -57,11 +58,6 @@
> #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
> #define PCIE_ATU_UPPER_TARGET 0x91C
>
> -/* LUT registers */
> -#define PCIE_LUT_BASE 0x80000
> -#define PCIE_LUT_LCTRL0 0x7F8
> -#define PCIE_LUT_DBG 0x7FC
> -
> #define PCIE_DBI_RO_WR_EN 0x8bc
>
> #define PCIE_LINK_CAP 0x7c
> @@ -157,12 +153,12 @@ static int ls_pcie_link_state(struct ls_pcie *pcie)
>
> return 1;
> }
> -#else
> +#elif defined(CONFIG_FSL_LAYERSCAPE)
> static int ls_pcie_link_state(struct ls_pcie *pcie)
> {
> u32 state;
>
> - state = readl(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
> + state = pex_lut_in32(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
> LTSSM_STATE_MASK;
> if (state < LTSSM_PCIE_L0) {
> debug("....PCIe link error. LTSSM=0x%02x.\n", state);
> @@ -466,16 +462,20 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie,
> struct ls_pcie_info *info)
>
> for (pf = 0; pf < PCIE_PF_NUM; pf++) {
> for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
> +#ifdef CONFIG_FSL_LAYERSCAPE
> writel(PCIE_LCTRL0_VAL(pf, vf),
> pcie->dbi + PCIE_LUT_BASE +
> PCIE_LUT_LCTRL0);
> +#endif
It looks really weird to have "#ifdef CONFIG_FSL_LAYERSCAPE" inside a file
whose name suggests is layerscape-specific. What chips use this file that
are not CONFIG_FSL_LAYERSCAPE?
-Scott
next prev parent reply other threads:[~2015-11-04 23:45 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-02 11:15 [U-Boot] [Patch V2 0/4] add LS1043AQDS support Gong Qianyu
2015-11-02 11:15 ` [U-Boot] [Patch V2 1/4] pci/layerscape: add support for LS1043A PCIe LUT register access Gong Qianyu
2015-11-04 23:45 ` Scott Wood [this message]
2015-11-05 5:00 ` Bin Meng
2015-11-06 0:17 ` Simon Glass
2015-11-02 11:15 ` [U-Boot] [Patch V2 2/4] armv8/ls1043ardb: dts: add dtb support Gong Qianyu
2015-11-04 23:50 ` Scott Wood
2015-11-06 10:30 ` Gong Q.Y.
2015-11-02 11:15 ` [U-Boot] [Patch V2 3/4] armv8/ls1043aqds: add LS1043AQDS board support Gong Qianyu
2015-11-04 23:54 ` Scott Wood
2015-11-02 11:15 ` [U-Boot] [Patch V2 4/4] armv8/ls1043aqds: dts: add dtb support Gong Qianyu
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