From: Joakim Tjernlund <joakim.tjernlund@transmode.se>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v1 0/7] Enable high speed and heavy load for DDR4 for LSCH3
Date: Thu, 5 Nov 2015 08:03:53 +0000 [thread overview]
Message-ID: <1446710633.21216.119.camel@transmode.se> (raw)
In-Reply-To: <1446660203-18047-1-git-send-email-yorksun@freescale.com>
On Wed, 2015-11-04 at 10:03 -0800, York Sun wrote:
> This patch set revises the DDR driver to support higher speed for DDR4
> under heavy load (two dual-rank DIMMs) for four-chipselect interleaving.
> Single quad-rank DIMM is not supported yet.
Hi York
Seeing these patches reminds me about something I have been mening to ask,
Is it possible init the ddr controller/ddr ram (using ECC also) but
still retain (parts of) memory contents?
I am looking at keeping data at the end of memory when performing a
warm start, but still init the controll/ddr ram (without D_INIT set).
This way one could pick up any changes to DDR timing if needed.
Before reboot, ddr ram is set to Self Refresh(SR).
Jocke
next prev parent reply other threads:[~2015-11-05 8:03 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-04 18:03 [U-Boot] [PATCH v1 0/7] Enable high speed and heavy load for DDR4 for LSCH3 York Sun
2015-11-04 18:03 ` [U-Boot] [PATCH v1 1/7] driver/ddr/fsl: Update DDR4 RTT values York Sun
2015-11-04 18:03 ` [U-Boot] [PATCH v1 2/7] driver/ddr/fsl: Update DDR4 MR6 for Vref range York Sun
2015-11-04 18:03 ` [U-Boot] [PATCH v1 3/7] driver/ddr/fsl: Update MR5 RTT park York Sun
2015-11-04 18:03 ` [U-Boot] [PATCH v1 4/7] driver/ddr/fsl: Update workaround for A008511 for vref range York Sun
2015-11-04 18:03 ` [U-Boot] [PATCH v1 5/7] driver/ddr/fsl: Update timing config for heavy load York Sun
2015-11-04 18:03 ` [U-Boot] [PATCH v1 6/7] armv8/ls2085aqds: Update DDR settings for four chip-select case York Sun
2015-11-04 18:03 ` [U-Boot] [PATCH v1 7/7] armv8/ls2085ardb: " York Sun
2015-11-05 8:03 ` Joakim Tjernlund [this message]
2015-11-05 8:23 ` [U-Boot] [PATCH v1 0/7] Enable high speed and heavy load for DDR4 for LSCH3 Yuantian Tang
2015-11-05 9:55 ` Joakim Tjernlund
2015-11-05 17:42 ` York Sun
2015-11-05 18:19 ` Joakim Tjernlund
2015-11-05 18:29 ` York Sun
2015-11-05 19:53 ` Joakim Tjernlund
2015-11-05 20:47 ` York Sun
2015-11-12 7:35 ` Joakim Tjernlund
2015-11-12 16:43 ` York Sun
2015-11-06 2:24 ` Yuantian Tang
2015-11-06 11:10 ` Joakim Tjernlund
2015-12-15 0:41 ` York Sun
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